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It's required to fix EDMA based transfer hangs observed on rockchip rk3188. Signed-off-by: Alexander Kochetkov --- drivers/mmc/host/dw_mmc.c | 4 ++++ drivers/mmc/host/dw_mmc.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 80dc2fd..d3ecee9 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2819,6 +2819,7 @@ static int dw_mci_init_slot_caps(struct dw_mci_slot *slot) static int dw_mci_init_slot(struct dw_mci *host) { + const struct dw_mci_drv_data *drv_data = host->drv_data; struct mmc_host *mmc; struct dw_mci_slot *slot; int ret; @@ -2876,6 +2877,9 @@ static int dw_mci_init_slot(struct dw_mci *host) mmc->max_seg_size = mmc->max_req_size; } + if (drv_data && drv_data->init_slot) + drv_data->init_slot(host); + dw_mci_get_cd(mmc); ret = mmc_add_host(mmc); diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h index 46e9f8e..de51c59 100644 --- a/drivers/mmc/host/dw_mmc.h +++ b/drivers/mmc/host/dw_mmc.h @@ -548,6 +548,7 @@ struct dw_mci_slot { * @caps: mmc subsystem specified capabilities of the controller(s). * @num_caps: number of capabilities specified by @caps. * @init: early implementation specific initialization. + * @init_slot: platform specific slot initialization. * @set_ios: handle bus specific extensions. * @parse_dt: parse implementation specific device tree properties. * @execute_tuning: implementation specific tuning procedure. @@ -560,6 +561,7 @@ struct dw_mci_drv_data { unsigned long *caps; u32 num_caps; int (*init)(struct dw_mci *host); + void (*init_slot)(struct dw_mci *host); void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); int (*parse_dt)(struct dw_mci *host); int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode); From patchwork Wed Mar 20 17:48:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Kochetkov X-Patchwork-Id: 10862343 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 99A281575 for ; Wed, 20 Mar 2019 17:48:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7818A29E4A for ; Wed, 20 Mar 2019 17:48:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6C20029E5D; Wed, 20 Mar 2019 17:48:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2243E29E40 for ; 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I've made test, that 100% reproduce the error. I found, that setting max_segs parameter to 1 fix the problem. I guess the problem is hardware related and relates to DMA controller implementation for rk3188. Probably it can relates to missed FLUSHP, see commit 271e1b86e691 ("dmaengine: pl330: add quirk for broken no flushp"). It is possible that pl330 and dw_mmc become out of sync then pl330 driver switch from one scatterlist to another. If we limit scatterlist size to 1, we can avoid switching scatterlists and avoid hardware problem. Setting max_segs to 1 tells mmc core to use maximum one scatterlist for one transfer. I guess that all other rk3xxx chips that lacks FLUSHP also affected by the problem. So I made fix for all rk3xxx chips from rk2928 to rk3188. Signed-off-by: Alexander Kochetkov --- drivers/mmc/host/dw_mmc-rockchip.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c index 8c86a80..2eed922 100644 --- a/drivers/mmc/host/dw_mmc-rockchip.c +++ b/drivers/mmc/host/dw_mmc-rockchip.c @@ -292,6 +292,24 @@ static int dw_mci_rk3288_parse_dt(struct dw_mci *host) return 0; } +static void dw_mci_rk2928_init_slot(struct dw_mci *host) +{ + struct mmc_host *mmc = host->slot->mmc; + + if (host->use_dma == TRANS_MODE_EDMAC) { + /* + * Using max_segs > 1 leads to rare EDMA transfer hangs + * resulting in HTO errors. + */ + mmc->max_segs = 1; + mmc->max_blk_size = 65535; + mmc->max_blk_count = 64 * 512; + mmc->max_req_size = + mmc->max_blk_size * mmc->max_blk_count; + mmc->max_seg_size = mmc->max_req_size; + } +} + static int dw_mci_rockchip_init(struct dw_mci *host) { /* It is slot 8 on Rockchip SoCs */ @@ -314,6 +332,7 @@ static int dw_mci_rockchip_init(struct dw_mci *host) static const struct dw_mci_drv_data rk2928_drv_data = { .init = dw_mci_rockchip_init, + .init_slot = dw_mci_rk2928_init_slot, }; static const struct dw_mci_drv_data rk3288_drv_data = {