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This brings the BSP more in line with the APs. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/setup.c | 2 ++ xen/arch/x86/traps.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index bde5d75ea6ab..718297ca541a 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -2024,6 +2024,8 @@ void asmlinkage __init noreturn __start_xen(void) trap_init(); + cpu_init(); + rcu_init(); early_time_init(); diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index df1155bfb673..a89f4f4f34ea 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1938,8 +1938,6 @@ void __init trap_init(void) l1e_from_pfn(virt_to_mfn(boot_compat_gdt), __PAGE_HYPERVISOR_RW); percpu_traps_init(); - - cpu_init(); } void asm_domain_crash_synchronous(unsigned long addr) From patchwork Mon Mar 17 19:20:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 14019903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D44FC35FFA for ; Mon, 17 Mar 2025 19:20:45 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.918003.1322765 (Exim 4.92) (envelope-from ) id 1tuG0l-0005dJ-Mb; Mon, 17 Mar 2025 19:20:31 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 918003.1322765; Mon, 17 Mar 2025 19:20:31 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tuG0l-0005ch-GC; Mon, 17 Mar 2025 19:20:31 +0000 Received: by outflank-mailman (input) for mailman id 918003; Mon, 17 Mar 2025 19:20:30 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tuG0j-0005ZB-Us for xen-devel@lists.xenproject.org; Mon, 17 Mar 2025 19:20:29 +0000 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [2a00:1450:4864:20::329]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e2c6be57-0364-11f0-9aba-95dc52dad729; Mon, 17 Mar 2025 20:20:28 +0100 (CET) Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-43690d4605dso17564045e9.0 for ; Mon, 17 Mar 2025 12:20:28 -0700 (PDT) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. 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No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/acpi/power.c | 1 + xen/arch/x86/include/asm/system.h | 1 - xen/arch/x86/include/asm/traps.h | 2 ++ xen/arch/x86/setup.c | 1 + xen/arch/x86/smpboot.c | 1 + xen/arch/x86/traps-setup.c | 15 +++++++++++++++ xen/arch/x86/traps.c | 8 -------- 7 files changed, 20 insertions(+), 9 deletions(-) diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c index fe70257864e1..3196a33b1918 100644 --- a/xen/arch/x86/acpi/power.c +++ b/xen/arch/x86/acpi/power.c @@ -31,6 +31,7 @@ #include #include #include +#include #include diff --git a/xen/arch/x86/include/asm/system.h b/xen/arch/x86/include/asm/system.h index 73cb16ca68d6..73364056c702 100644 --- a/xen/arch/x86/include/asm/system.h +++ b/xen/arch/x86/include/asm/system.h @@ -266,7 +266,6 @@ static inline int local_irq_is_enabled(void) void trap_init(void); void init_idt_traps(void); void load_system_tables(void); -void percpu_traps_init(void); void subarch_percpu_traps_init(void); #endif diff --git a/xen/arch/x86/include/asm/traps.h b/xen/arch/x86/include/asm/traps.h index 01ef362edc8c..825f7441c86e 100644 --- a/xen/arch/x86/include/asm/traps.h +++ b/xen/arch/x86/include/asm/traps.h @@ -7,6 +7,8 @@ #ifndef ASM_TRAP_H #define ASM_TRAP_H +void percpu_traps_init(void); + const char *vector_name(unsigned int vec); #endif /* ASM_TRAP_H */ diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 718297ca541a..b092106ccca5 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -56,6 +56,7 @@ #include #include #include +#include #include diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c index b63a9ce13e0a..54207e6d8830 100644 --- a/xen/arch/x86/smpboot.c +++ b/xen/arch/x86/smpboot.c @@ -41,6 +41,7 @@ #include #include #include +#include uint32_t __ro_after_init trampoline_phys; enum ap_boot_method __read_mostly ap_boot_method = AP_BOOT_NORMAL; diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c index 3ee28319584d..fa78a35a7ebf 100644 --- a/xen/arch/x86/traps-setup.c +++ b/xen/arch/x86/traps-setup.c @@ -3,5 +3,20 @@ * Configuration of event handling for all CPUs. */ #include +#include +#include +#include DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt); + +/* + * Set up per-CPU linkage registers for exception, interrupt and syscall + * handling. + */ +void percpu_traps_init(void) +{ + subarch_percpu_traps_init(); + + if ( cpu_has_xen_lbr ) + wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR); +} diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index a89f4f4f34ea..29d7e4123f90 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1864,14 +1864,6 @@ void asmlinkage do_entry_CP(struct cpu_user_regs *regs) panic("CONTROL-FLOW PROTECTION FAULT: #CP[%04x] %s\n", ec, err); } -void percpu_traps_init(void) -{ - subarch_percpu_traps_init(); - - if ( cpu_has_xen_lbr ) - wrmsrl(MSR_IA32_DEBUGCTLMSR, IA32_DEBUGCTLMSR_LBR); -} - void nocall entry_PF(void); void __init init_idt_traps(void) From patchwork Mon Mar 17 19:20:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 14019905 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BC0CC28B28 for ; Mon, 17 Mar 2025 19:20:45 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.918004.1322770 (Exim 4.92) (envelope-from ) id 1tuG0m-0005mH-2T; Mon, 17 Mar 2025 19:20:32 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 918004.1322770; Mon, 17 Mar 2025 19:20:32 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tuG0l-0005l0-Sf; Mon, 17 Mar 2025 19:20:31 +0000 Received: by outflank-mailman (input) for mailman id 918004; Mon, 17 Mar 2025 19:20:30 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tuG0k-0005ZB-JE for xen-devel@lists.xenproject.org; Mon, 17 Mar 2025 19:20:30 +0000 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [2a00:1450:4864:20::32b]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e36cedf1-0364-11f0-9aba-95dc52dad729; Mon, 17 Mar 2025 20:20:29 +0100 (CET) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-43cf0d787eeso26882595e9.3 for ; Mon, 17 Mar 2025 12:20:29 -0700 (PDT) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. [92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fe292d0sm113505845e9.20.2025.03.17.12.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 12:20:28 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e36cedf1-0364-11f0-9aba-95dc52dad729 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1742239229; x=1742844029; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mr8DI3nBv401BCL/XAx6lN4oA/5pcywS2sI15DoEEvo=; b=sdO54gCBM6krVT/cbawWHix6XS9Js0hRXOGmqc9QOd17VaGPTGLe5fb5heOoRkTxYN WpVloRBRtvobkI4MS0Xi3VjIZ2NXDXGj9Qqc913lg62FHL/+qQFvkGGoVwVeqFlnQsdx YYGQeyos3yEsZNoIqHPY2zSKeYoGcSoKP8fMQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742239229; x=1742844029; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mr8DI3nBv401BCL/XAx6lN4oA/5pcywS2sI15DoEEvo=; b=SzDEcY6MSBC3MXIH5hJaegH+JPRqR0CGXbwaCHak9MJfZvTcamkufV/9blVrM3OMyY zEQWGnbquPZPR4/XsJIw+rMJCKGSm/EQjzhbELf3jDfxXzfGnJRRe2eQAgHZDNeZBYBc c9f1M9f5CWEo5U4UydzN6t3i8YnJJ2t3PYZ8KhECcC88vihn+UC0ULrWw/ZR12lJFXUa tIwyVUah/RUOvpbiMgUks/l2N0WSwksebSvp18XQVPF7BM6oveb5XIW2DNsM1o3zJvLL 2SJaXwKxGtJhHs2Fwnkk/5uG17srXsVDXqfuYF5Wzkkyz4kmguAsVK651Brys9R8zIZv xTaA== X-Gm-Message-State: AOJu0YyFGroSt+XtNj81JMMHsnXmD4I0dE/+GTDxcQ1WG3Ew3+OBzFZQ YkS7UKlTmCxwcBl7GfTA8voGCVs0NumVyodNju5SPGw5+fbD1HSpXmER2xq5PuWod/7Nr/jXz9I y X-Gm-Gg: ASbGncv2SLBx9c5ZZztVYJj4QltKGX7+oxtUCPjp0lGUtRXxs+b2aQ65gapTfAJYJGk JhZdsBv+mU3n8P484/2Mx63g2hXY7oB8bt4/cE90Sef7hp9n0XupcAOGU7SitKev+L4Jozwi5+/ x9/81ArgKnE9FgdoPt3OmO+L9biqEK+G5DsV56meaaudp6GGxNYWYVxLzGFGnHNN/h/AivK52Nw V+3UiU6FVYZzy2w9oc6xuUboTaKDQioNeZ/qVgkVabEtSCWx+n4k9MGMegTID9ESPWY9j7OYmLw SWO/m/rtuXHEY2RqP2Mn2G4M9Vx8Tiv803cHQdtBohG22zpeF5OEmCLfwFyHdyDBi7SDVpJZg9I 7dmi6B/qRfnaaVQ0j3iotRtV+ X-Google-Smtp-Source: AGHT+IFrmZrN+A0yETYgzcrUEIuIBFCET8LfBxmDWDE3Gwl7zIbPOM5HVlusn95h1j3ItZ2R4zkfSw== X-Received: by 2002:a05:600c:4e47:b0:43c:ef55:f1e8 with SMTP id 5b1f17b1804b1-43d285684famr82499145e9.13.1742239228873; Mon, 17 Mar 2025 12:20:28 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 3/4] x86/traps: Move trap_init() into traps-setup.c Date: Mon, 17 Mar 2025 19:20:22 +0000 Message-Id: <20250317192023.568432-4-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250317192023.568432-1-andrew.cooper3@citrix.com> References: <20250317192023.568432-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 ... and rename to traps_init() for consistency. Move the declaration from asm/system.h into asm/traps.h. This also involves moving init_ler() and variables. Move the declaration of ler_msr from asm/msr.h to asm/traps.h. No functional change. Signed-off-by: Andrew Cooper Acked-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/include/asm/msr.h | 2 - xen/arch/x86/include/asm/system.h | 1 - xen/arch/x86/include/asm/traps.h | 3 ++ xen/arch/x86/setup.c | 2 +- xen/arch/x86/traps-setup.c | 66 +++++++++++++++++++++++++++++++ xen/arch/x86/traps.c | 61 ---------------------------- 6 files changed, 70 insertions(+), 65 deletions(-) diff --git a/xen/arch/x86/include/asm/msr.h b/xen/arch/x86/include/asm/msr.h index 7b00a4db5d48..549d40b404cb 100644 --- a/xen/arch/x86/include/asm/msr.h +++ b/xen/arch/x86/include/asm/msr.h @@ -279,8 +279,6 @@ static inline void write_efer(uint64_t val) wrmsrl(MSR_EFER, val); } -extern unsigned int ler_msr; - DECLARE_PER_CPU(uint32_t, tsc_aux); /* Lazy update of MSR_TSC_AUX */ diff --git a/xen/arch/x86/include/asm/system.h b/xen/arch/x86/include/asm/system.h index 73364056c702..1bf6bd026852 100644 --- a/xen/arch/x86/include/asm/system.h +++ b/xen/arch/x86/include/asm/system.h @@ -263,7 +263,6 @@ static inline int local_irq_is_enabled(void) #define BROKEN_ACPI_Sx 0x0001 #define BROKEN_INIT_AFTER_S1 0x0002 -void trap_init(void); void init_idt_traps(void); void load_system_tables(void); void subarch_percpu_traps_init(void); diff --git a/xen/arch/x86/include/asm/traps.h b/xen/arch/x86/include/asm/traps.h index 825f7441c86e..3d30aa6738d4 100644 --- a/xen/arch/x86/include/asm/traps.h +++ b/xen/arch/x86/include/asm/traps.h @@ -7,8 +7,11 @@ #ifndef ASM_TRAP_H #define ASM_TRAP_H +void traps_init(void); void percpu_traps_init(void); +extern unsigned int ler_msr; + const char *vector_name(unsigned int vec); #endif /* ASM_TRAP_H */ diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index b092106ccca5..5e2411a008f5 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -2023,7 +2023,7 @@ void asmlinkage __init noreturn __start_xen(void) &this_cpu(stubs).mfn); BUG_ON(!this_cpu(stubs.addr)); - trap_init(); + traps_init(); /* Needs stubs allocated. */ cpu_init(); diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c index fa78a35a7ebf..1a7b42c14bf2 100644 --- a/xen/arch/x86/traps-setup.c +++ b/xen/arch/x86/traps-setup.c @@ -2,6 +2,9 @@ /* * Configuration of event handling for all CPUs. */ +#include +#include + #include #include #include @@ -9,6 +12,69 @@ DEFINE_PER_CPU_READ_MOSTLY(idt_entry_t *, idt); +/* LastExceptionFromIP on this hardware. Zero if LER is not in use. */ +unsigned int __ro_after_init ler_msr; +static bool __initdata opt_ler; +boolean_param("ler", opt_ler); + +void nocall entry_PF(void); + +static void __init init_ler(void) +{ + unsigned int msr = 0; + + if ( !opt_ler ) + return; + + /* + * Intel Pentium 4 is the only known CPU to not use the architectural MSR + * indicies. + */ + switch ( boot_cpu_data.x86_vendor ) + { + case X86_VENDOR_INTEL: + if ( boot_cpu_data.x86 == 0xf ) + { + msr = MSR_P4_LER_FROM_LIP; + break; + } + fallthrough; + case X86_VENDOR_AMD: + case X86_VENDOR_HYGON: + msr = MSR_IA32_LASTINTFROMIP; + break; + } + + if ( msr == 0 ) + { + printk(XENLOG_WARNING "LER disabled: failed to identify MSRs\n"); + return; + } + + ler_msr = msr; + setup_force_cpu_cap(X86_FEATURE_XEN_LBR); +} + +/* + * Configure complete exception, interrupt and syscall handling. + */ +void __init traps_init(void) +{ + /* Replace early pagefault with real pagefault handler. */ + _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF); + + init_ler(); + + /* Cache {,compat_}gdt_l1e now that physically relocation is done. */ + this_cpu(gdt_l1e) = + l1e_from_pfn(virt_to_mfn(boot_gdt), __PAGE_HYPERVISOR_RW); + if ( IS_ENABLED(CONFIG_PV32) ) + this_cpu(compat_gdt_l1e) = + l1e_from_pfn(virt_to_mfn(boot_compat_gdt), __PAGE_HYPERVISOR_RW); + + percpu_traps_init(); +} + /* * Set up per-CPU linkage registers for exception, interrupt and syscall * handling. diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 29d7e4123f90..79d92f21acf5 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -107,12 +107,6 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_page, tss_page); static int debug_stack_lines = 20; integer_param("debug_stack_lines", debug_stack_lines); -static bool __initdata opt_ler; -boolean_param("ler", opt_ler); - -/* LastExceptionFromIP on this hardware. Zero if LER is not in use. */ -unsigned int __ro_after_init ler_msr; - const unsigned int nmi_cpu; #define stack_words_per_line 4 @@ -1864,8 +1858,6 @@ void asmlinkage do_entry_CP(struct cpu_user_regs *regs) panic("CONTROL-FLOW PROTECTION FAULT: #CP[%04x] %s\n", ec, err); } -void nocall entry_PF(void); - void __init init_idt_traps(void) { /* Specify dedicated interrupt stacks for NMI, #DF, and #MC. */ @@ -1879,59 +1871,6 @@ void __init init_idt_traps(void) this_cpu(compat_gdt) = boot_compat_gdt; } -static void __init init_ler(void) -{ - unsigned int msr = 0; - - if ( !opt_ler ) - return; - - /* - * Intel Pentium 4 is the only known CPU to not use the architectural MSR - * indicies. - */ - switch ( boot_cpu_data.x86_vendor ) - { - case X86_VENDOR_INTEL: - if ( boot_cpu_data.x86 == 0xf ) - { - msr = MSR_P4_LER_FROM_LIP; - break; - } - fallthrough; - case X86_VENDOR_AMD: - case X86_VENDOR_HYGON: - msr = MSR_IA32_LASTINTFROMIP; - break; - } - - if ( msr == 0 ) - { - printk(XENLOG_WARNING "LER disabled: failed to identify MSRs\n"); - return; - } - - ler_msr = msr; - setup_force_cpu_cap(X86_FEATURE_XEN_LBR); -} - -void __init trap_init(void) -{ - /* Replace early pagefault with real pagefault handler. */ - _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF); - - init_ler(); - - /* Cache {,compat_}gdt_l1e now that physically relocation is done. */ - this_cpu(gdt_l1e) = - l1e_from_pfn(virt_to_mfn(boot_gdt), __PAGE_HYPERVISOR_RW); - if ( IS_ENABLED(CONFIG_PV32) ) - this_cpu(compat_gdt_l1e) = - l1e_from_pfn(virt_to_mfn(boot_compat_gdt), __PAGE_HYPERVISOR_RW); - - percpu_traps_init(); -} - void asm_domain_crash_synchronous(unsigned long addr) { /* From patchwork Mon Mar 17 19:20:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Cooper X-Patchwork-Id: 14019904 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4B729C35FF9 for ; Mon, 17 Mar 2025 19:20:45 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.918005.1322788 (Exim 4.92) (envelope-from ) id 1tuG0n-0006Fl-9w; Mon, 17 Mar 2025 19:20:33 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 918005.1322788; Mon, 17 Mar 2025 19:20:33 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tuG0n-0006Fa-5k; Mon, 17 Mar 2025 19:20:33 +0000 Received: by outflank-mailman (input) for mailman id 918005; Mon, 17 Mar 2025 19:20:31 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tuG0l-0005ZB-L0 for xen-devel@lists.xenproject.org; Mon, 17 Mar 2025 19:20:31 +0000 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [2a00:1450:4864:20::432]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e43407ae-0364-11f0-9aba-95dc52dad729; Mon, 17 Mar 2025 20:20:31 +0100 (CET) Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-3995ff6b066so1181958f8f.3 for ; Mon, 17 Mar 2025 12:20:31 -0700 (PDT) Received: from andrewcoop.eng.citrite.net (host-92-26-98-202.as13285.net. [92.26.98.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fe292d0sm113505845e9.20.2025.03.17.12.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Mar 2025 12:20:29 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: e43407ae-0364-11f0-9aba-95dc52dad729 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1742239230; x=1742844030; darn=lists.xenproject.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JfALmh2Mta205aGWnBqRuhdKfESvLlwk5s7oemAqxsg=; b=FHEd6ngtfM5ErNhdHFIPyjLkJm0JLcKhbP9dIilgCRoP+5W9US9scxBx1G/+AAKrNx hLFM5/4apzOeD2mqK95wD5GOedfJqttePoR1bXELMP14H7ciBfzcyJbDZ2uw14M/2+MF v54K2CG7jfkGSW4E3tQqSc/WVnVzuyVHezc98= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1742239230; x=1742844030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JfALmh2Mta205aGWnBqRuhdKfESvLlwk5s7oemAqxsg=; b=igQLSJb5BGm+lMYUiPZnZkbRx2J4jgWvsVH+Zjt3xYmy/aUoGRgEJm7ZxjhD7sEmLC 5nVLDMnofzo8sXFATWFcF2/1zEv6wd3AUej8EPSu6irs9YDm8eK97wlG+if/W3oMYhs3 6eBl99UQdasFYoatLUtxvmg2WmRoac9NWSkebQgYNNvuhqqF4oFwPXMtTVpRamqcafgW SpPRZbkNj/FbufjFNUrM3flKRrErC53Ryj9Wzz1+DWr4/7P1JFRB43NkblG9HmC7CFpl GZng7isRPfhxMy4In24IIoQNu9pJWjYaH0R6tKbabkVJ2S80+u71bDfKVWfH1ocspAFo QO7g== X-Gm-Message-State: AOJu0Ywl/BteNwUP2pzpNuadcML9AHEUwV3Rc40poMVvk7SreB0M80cz Ln9wHrcwEz82GPAEu96b3Kt0JgrvbYAl94WZBBbIpe22a1Yie1dNnv28z1UGG8fgrgC6m67n51B 8 X-Gm-Gg: ASbGncvcVA+Brn2NJq7oCmmtnPnGKsBj0qUARKYU6njAI/TYfci5ixVcw5Vvxc8gAXQ KhqvU0d+2SNkOBtMEniTcenPtIqdJ3UQey+2RTCa6XbxsMmBrXulZhhivns2aJjsofbateFfuKY YiHpOfwBfGkLbDE9dEoYY350En7AKiLs9DMG87QNlrYurJJFPA0YZ2evcySxoeHClQB+C8CCoLz yBuoeT32RhYpF71mcgovfhIELIXRGafHxQTGIJ0+zxOH8OukjMPBKh3TNe3QCK7d1VY70w74xH4 n8Is7FLxzVW1G47xLQ8zELM5xF6xBEOq7fVfncyy92yjMkv+xMCWOvk8FIcjnYLKoC0brGgbfYL pF2FcejlouqSsrcZhil/gGaS+ X-Google-Smtp-Source: AGHT+IH6SnuKA9Qh36JS9CV63sf4fZQsWn8byy++oyL1vIa/RK/cvvQBD22JJPW6Mangixbx9yWaZw== X-Received: by 2002:a05:6000:4027:b0:391:1222:b444 with SMTP id ffacd0b85a97d-3971e9720d7mr13011538f8f.20.1742239230150; Mon, 17 Mar 2025 12:20:30 -0700 (PDT) From: Andrew Cooper To: Xen-devel Cc: Andrew Cooper , Jan Beulich , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 4/4] x86/traps: Introduce early_traps_init() and simplify setup Date: Mon, 17 Mar 2025 19:20:23 +0000 Message-Id: <20250317192023.568432-5-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250317192023.568432-1-andrew.cooper3@citrix.com> References: <20250317192023.568432-1-andrew.cooper3@citrix.com> MIME-Version: 1.0 Something I overlooked when last cleaning up exception handling is that a TSS is not necessary if IST isn't configured, and IST isn't necessary until we're running guest code. Introduce early_traps_init() which is far more minimal than init_idt_traps(); bsp_ist[] is constructed without IST settings, so all early_traps_init() needs to do is load the IDT, and invalidate TR/LDTR. Put the remaining logic into traps_init(), later on boot. Note that load_system_tables() already contains enable_each_ist(), so the call is simply dropped. This removes some complexity prior to having exception support, and lays the groundwork to not even allocate a TSS when using FRED. No practical change. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- CC: Jan Beulich CC: Roger Pau Monné --- xen/arch/x86/include/asm/system.h | 1 - xen/arch/x86/include/asm/traps.h | 1 + xen/arch/x86/setup.c | 3 +-- xen/arch/x86/traps-setup.c | 32 +++++++++++++++++++++++++++++++ xen/arch/x86/traps.c | 13 ------------- 5 files changed, 34 insertions(+), 16 deletions(-) diff --git a/xen/arch/x86/include/asm/system.h b/xen/arch/x86/include/asm/system.h index 1bf6bd026852..8ceaaf45d1a0 100644 --- a/xen/arch/x86/include/asm/system.h +++ b/xen/arch/x86/include/asm/system.h @@ -263,7 +263,6 @@ static inline int local_irq_is_enabled(void) #define BROKEN_ACPI_Sx 0x0001 #define BROKEN_INIT_AFTER_S1 0x0002 -void init_idt_traps(void); void load_system_tables(void); void subarch_percpu_traps_init(void); diff --git a/xen/arch/x86/include/asm/traps.h b/xen/arch/x86/include/asm/traps.h index 3d30aa6738d4..72c33a33e283 100644 --- a/xen/arch/x86/include/asm/traps.h +++ b/xen/arch/x86/include/asm/traps.h @@ -7,6 +7,7 @@ #ifndef ASM_TRAP_H #define ASM_TRAP_H +void early_traps_init(void); void traps_init(void); void percpu_traps_init(void); diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index 5e2411a008f5..6a6ddc569500 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -1093,8 +1093,7 @@ void asmlinkage __init noreturn __start_xen(void) percpu_init_areas(); - init_idt_traps(); - load_system_tables(); + early_traps_init(); smp_prepare_boot_cpu(); sort_exception_tables(); diff --git a/xen/arch/x86/traps-setup.c b/xen/arch/x86/traps-setup.c index 1a7b42c14bf2..67a6fda89ad9 100644 --- a/xen/arch/x86/traps-setup.c +++ b/xen/arch/x86/traps-setup.c @@ -55,6 +55,31 @@ static void __init init_ler(void) setup_force_cpu_cap(X86_FEATURE_XEN_LBR); } +/* + * Configure basic exception handling. This is prior to parsing the command + * line or configuring a console, and needs to be as simple as possible. + * + * boot_gdt is already loaded, and bsp_idt[] is constructed without IST + * settings, so we don't need a TSS configured yet. + * + * Load bsp_idt[], and invalidate the TSS and LDT. + */ +void __init early_traps_init(void) +{ + const struct desc_ptr idtr = { + .base = (unsigned long)bsp_idt, + .limit = sizeof(bsp_idt) - 1, + }; + + lidt(&idtr); + + _set_tssldt_desc(boot_gdt + TSS_ENTRY - FIRST_RESERVED_GDT_ENTRY, + 0, 0, SYS_DESC_tss_avail); + + ltr(TSS_SELECTOR); + lldt(0); +} + /* * Configure complete exception, interrupt and syscall handling. */ @@ -63,6 +88,13 @@ void __init traps_init(void) /* Replace early pagefault with real pagefault handler. */ _update_gate_addr_lower(&bsp_idt[X86_EXC_PF], entry_PF); + this_cpu(idt) = bsp_idt; + this_cpu(gdt) = boot_gdt; + if ( IS_ENABLED(CONFIG_PV32) ) + this_cpu(compat_gdt) = boot_compat_gdt; + + load_system_tables(); + init_ler(); /* Cache {,compat_}gdt_l1e now that physically relocation is done. */ diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 79d92f21acf5..25e0d5777e6e 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -1858,19 +1858,6 @@ void asmlinkage do_entry_CP(struct cpu_user_regs *regs) panic("CONTROL-FLOW PROTECTION FAULT: #CP[%04x] %s\n", ec, err); } -void __init init_idt_traps(void) -{ - /* Specify dedicated interrupt stacks for NMI, #DF, and #MC. */ - enable_each_ist(bsp_idt); - - /* CPU0 uses the master IDT. */ - this_cpu(idt) = bsp_idt; - - this_cpu(gdt) = boot_gdt; - if ( IS_ENABLED(CONFIG_PV32) ) - this_cpu(compat_gdt) = boot_compat_gdt; -} - void asm_domain_crash_synchronous(unsigned long addr) { /*