From patchwork Fri Mar 21 16:38:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14025760 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5B49322D4E2; Fri, 21 Mar 2025 16:38:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742575120; cv=none; b=PowJTGNLG9h8VaQPtuhgKzlwbpQkWZ4RuJCRX8HAuY1UdAbvrI/tMRoiq8fwjjJs3CD/sXsIPFnw9XGT53hlUhHUM4kWM/VIAFFcSs49ZS8sHbGsdGpS08DNoos3lozM6ZFPd80dDYJS1030Q6lM0NJxtEDFIBWVJEoxX8G/SLA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742575120; c=relaxed/simple; bh=xPNYg3cMNd2hepZk+/icfw/kZYS6o4UEMPjYycNaUMA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=II0Tku2xV0/GIhokea2jovrm7e38RGE25U6U2v9Kz9WQBUNefMv9x4sjPWGTwlLFkjYlumuSGY3yoBl44kTaYq9SCsdbKWy411IDh7l0EedD5sAeaGO9IWWPyGcMFrC0EGDHA6rzC7FEhGtibnDNRXzJDdy6fCTzvWpBrhT64xs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=RnevxSoX; arc=none smtp.client-ip=220.197.31.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="RnevxSoX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=97101 Q/idF1/FmnK1pczrU+vUH7afq9gW82c3qeXiAg=; b=RnevxSoXATKcnHrY6XFfF M11S3ewmOALXDkW0ayIEw0RGXuxo4YDQk+G7zgaKzO74rfnlL/Ug1wqWSM7suber eiyQh901WMbfYVrZLY2xn8NRuzB7HFjISQspf+RrvQjFQrC0jGA9daxBOxw/a2rV inunhjv2sDr/ytBcUn+tKg= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-0 (Coremail) with SMTP id _____wC30e7sld1nnmPrAw--.48109S3; Sat, 22 Mar 2025 00:38:05 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v5 1/4] PCI: Introduce generic capability search functions Date: Sat, 22 Mar 2025 00:38:00 +0800 Message-Id: <20250321163803.391056-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321163803.391056-1-18255117159@163.com> References: <20250321163803.391056-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wC30e7sld1nnmPrAw--.48109S3 X-Coremail-Antispam: 1Uf129KBjvJXoW3Wr1rGrWkArWUtF48uFWrAFb_yoW7GFWDpr ZYy3W5J3yrGF42qwsFvF4jyr15WrZ2qrWfAFZ7C34Fvw1Iy3WFgas29a45tF17AFsrWF13 JFW7trZYkr1DtaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zEMa0PUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWwwXo2fdjwDOpgAAs+ Existing controller drivers (e.g., DWC, custom out-of-tree drivers) duplicate logic for scanning PCI capability lists. This creates maintenance burdens and risks inconsistencies. To resolve this: Add pci_host_bridge_find_*capability() in drivers/pci/pci.c, accepting controller-specific read functions and device data as parameters. This approach: - Centralizes critical PCI capability scanning logic - Allows flexible adaptation to varied hardware access methods - Reduces future maintenance overhead - Aligns with kernel code reuse best practices Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v4: https://lore.kernel.org/linux-pci/20250321101710.371480-2-18255117159@163.com - Resolved [v4 1/4] compilation warning. - The patch commit message were modified. --- drivers/pci/pci.c | 86 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 16 ++++++++- 2 files changed, 101 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 869d204a70a3..5ed31d723a45 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -612,6 +612,92 @@ u16 pci_find_ext_capability(struct pci_dev *dev, int cap) } EXPORT_SYMBOL_GPL(pci_find_ext_capability); +/* + * These interfaces resemble the pci_find_*capability() interfaces, but these + * are for configuring host controllers, which are bridges *to* PCI devices but + * are not PCI devices themselves. + */ +static u8 __pci_host_bridge_find_next_cap(void *priv, + pci_host_bridge_read_cfg read_cfg, + u8 cap_ptr, u8 cap) +{ + u8 cap_id, next_cap_ptr; + u16 reg; + + if (!cap_ptr) + return 0; + + reg = read_cfg(priv, cap_ptr, 2); + cap_id = (reg & 0x00ff); + + if (cap_id > PCI_CAP_ID_MAX) + return 0; + + if (cap_id == cap) + return cap_ptr; + + next_cap_ptr = (reg & 0xff00) >> 8; + return __pci_host_bridge_find_next_cap(priv, read_cfg, next_cap_ptr, + cap); +} + +u8 pci_host_bridge_find_capability(void *priv, + pci_host_bridge_read_cfg read_cfg, u8 cap) +{ + u8 next_cap_ptr; + u16 reg; + + reg = read_cfg(priv, PCI_CAPABILITY_LIST, 2); + next_cap_ptr = (reg & 0x00ff); + + return __pci_host_bridge_find_next_cap(priv, read_cfg, next_cap_ptr, + cap); +} +EXPORT_SYMBOL_GPL(pci_host_bridge_find_capability); + +static u16 pci_host_bridge_find_next_ext_capability( + void *priv, pci_host_bridge_read_cfg read_cfg, u16 start, u8 cap) +{ + u32 header; + int ttl; + int pos = PCI_CFG_SPACE_SIZE; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + if (start) + pos = start; + + header = read_cfg(priv, pos, 4); + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + return 0; + + while (ttl-- > 0) { + if (PCI_EXT_CAP_ID(header) == cap && pos != start) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (pos < PCI_CFG_SPACE_SIZE) + break; + + header = read_cfg(priv, pos, 4); + } + + return 0; +} + +u16 pci_host_bridge_find_ext_capability(void *priv, + pci_host_bridge_read_cfg read_cfg, + u8 cap) +{ + return pci_host_bridge_find_next_ext_capability(priv, read_cfg, 0, cap); +} +EXPORT_SYMBOL_GPL(pci_host_bridge_find_ext_capability); + /** * pci_get_dsn - Read and return the 8-byte Device Serial Number * @dev: PCI device to query diff --git a/include/linux/pci.h b/include/linux/pci.h index 47b31ad724fa..e4e8d437a864 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1205,6 +1205,12 @@ u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap); u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap); u16 pci_find_ext_capability(struct pci_dev *dev, int cap); u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap); +typedef u32 (*pci_host_bridge_read_cfg)(void *priv, int where, int size); +u8 pci_host_bridge_find_capability(void *priv, + pci_host_bridge_read_cfg read_cfg, u8 cap); +u16 pci_host_bridge_find_ext_capability(void *priv, + pci_host_bridge_read_cfg read_cfg, + u8 cap); struct pci_bus *pci_find_next_bus(const struct pci_bus *from); u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap); u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec); @@ -2012,7 +2018,15 @@ static inline u8 pci_find_next_capability(struct pci_dev *dev, u8 post, int cap) { return 0; } static inline u16 pci_find_ext_capability(struct pci_dev *dev, int cap) { return 0; } - +typedef u32 (*pci_host_bridge_read_cfg)(void *priv, int where, int size); +static inline u8 +pci_host_bridge_find_capability(void *priv, pci_host_bridge_read_cfg read_cfg, + u8 cap); +{ return 0; } +static inline u16 +pci_host_bridge_find_ext_capability(void *priv, + pci_host_bridge_read_cfg read_cfg, u8 cap); +{ return 0; } static inline u64 pci_get_dsn(struct pci_dev *dev) { return 0; } From patchwork Fri Mar 21 16:38:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14025759 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E72F422D4D9; Fri, 21 Mar 2025 16:38:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742575119; cv=none; b=R8DxweyZA4DuYpC/iq7C6yePEmbql8IOybd77CP0kARoQvmMpe+TH/Y8iYaK0vTjz49SIRQgfvBciL1tlN2RGJ1J7z4gYfZw7nIqj5364scyzSR6PFfF/oEpHw1MS/QibZQVqYJ237U+OipDs43e432Qr+oEFyxBR6JIRwPpMR8= ARC-Message-Signature: i=1; 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d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=Estu5 Bssy54LqLpfEBxpENJ+dUh23iyReSwXS6S41qA=; b=Zo7IRVu6lC8rU3d1kGI3s A5BZQWnlWJhnwLYGxWgYaiN6i8wpIbscp2YWQMc5J1lUJS6IfRzrbW8ikz3zkbgY Ls02PqkMHpM8cVqUku+OA+nC1+jufj/SQ2CWfBEOnEmax37gqAGuJkyrP7CaBcxz hbB5zru3o11cgAx3KhlUNg= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-0 (Coremail) with SMTP id _____wC30e7sld1nnmPrAw--.48109S4; Sat, 22 Mar 2025 00:38:06 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v5 2/4] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities Date: Sat, 22 Mar 2025 00:38:01 +0800 Message-Id: <20250321163803.391056-3-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321163803.391056-1-18255117159@163.com> References: <20250321163803.391056-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wC30e7sld1nnmPrAw--.48109S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxWrW8Kr4DZr17uw4DCF48JFb_yoW5AFyrpa yrA3WYkFWrtr4Yqw4qvFnIyF15AF9xAFWxAa97GwnavF12krWYg340kaySqF1xArZF9F13 Kr4xtas5Cw1kJa7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zi8pnLUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWw8Xo2fdjwDOvQAAsm Since the PCI core is now exposing generic APIs for the host bridges to search for the PCIe capabilities, make use of them in the DWC driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v4: https://lore.kernel.org/linux-pci/20250321101710.371480-3-18255117159@163.com - The patch subject and commit message were modified. --- drivers/pci/controller/dwc/pcie-designware.c | 71 ++------------------ 1 file changed, 5 insertions(+), 66 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 145e7f579072..0329f233cf11 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -203,83 +203,22 @@ void dw_pcie_version_detect(struct dw_pcie *pci) pci->type = ver; } -/* - * These interfaces resemble the pci_find_*capability() interfaces, but these - * are for configuring host controllers, which are bridges *to* PCI devices but - * are not PCI devices themselves. - */ -static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, - u8 cap) +static u32 dwc_pcie_read_cfg(void *priv, int where, int size) { - u8 cap_id, next_cap_ptr; - u16 reg; - - if (!cap_ptr) - return 0; - - reg = dw_pcie_readw_dbi(pci, cap_ptr); - cap_id = (reg & 0x00ff); - - if (cap_id > PCI_CAP_ID_MAX) - return 0; + struct dw_pcie *pci = priv; - if (cap_id == cap) - return cap_ptr; - - next_cap_ptr = (reg & 0xff00) >> 8; - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return dw_pcie_read_dbi(pci, where, size); } u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) { - u8 next_cap_ptr; - u16 reg; - - reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); - next_cap_ptr = (reg & 0x00ff); - - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return pci_host_bridge_find_capability(pci, dwc_pcie_read_cfg, cap); } EXPORT_SYMBOL_GPL(dw_pcie_find_capability); -static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, - u8 cap) -{ - u32 header; - int ttl; - int pos = PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (start) - pos = start; - - header = dw_pcie_readl_dbi(pci, pos); - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header == 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) == cap && pos != start) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - header = dw_pcie_readl_dbi(pci, pos); - } - - return 0; -} - u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) { - return dw_pcie_find_next_ext_capability(pci, 0, cap); + return pci_host_bridge_find_ext_capability(pci, dwc_pcie_read_cfg, cap); } EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); From patchwork Fri Mar 21 16:38:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14025761 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DDF2722D4F2; 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arc=none smtp.client-ip=117.135.210.3 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="S3r1+Qz5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=OjpOK cGhBDXFINK3Wem/YiCNyIuMSE6KlB+23VVaVHA=; b=S3r1+Qz56alnhogjCzuo6 6sIwig7VKxb6gU+dQzAk43vYvBMA6KpjOmBCMsvOmw+5BvDv0tBifxk8Im358ehO E3PUt9GvW5VL9+2re5Q5lH7TIZUpI89u1sGotnO/JdkolPoBaLrTIJKyRyezC0bm I3Xnw/zhZtWUu1P7qWo0wc= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-0 (Coremail) with SMTP id _____wC30e7sld1nnmPrAw--.48109S5; Sat, 22 Mar 2025 00:38:06 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v5 3/4] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities Date: Sat, 22 Mar 2025 00:38:02 +0800 Message-Id: <20250321163803.391056-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321163803.391056-1-18255117159@163.com> References: <20250321163803.391056-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wC30e7sld1nnmPrAw--.48109S5 X-Coremail-Antispam: 1Uf129KBjvJXoWxAFyftr45GFW7tw18Cw17ZFb_yoW5Xw1kpF WUCFyfCF1rJrW7uFs3Z3W5XF13tasay347t39ak34fZF17CF1UGFn2gFy5tFZIkrZFgr1f XF9rtFykKrn5tFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zR9FxbUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWw0Xo2fdjwDOzgAAsX Since the PCI core is now exposing generic APIs for the host bridges to search for the PCIe capabilities, make use of them in the CDNS driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v4: https://lore.kernel.org/linux-pci/20250321101710.371480-4-18255117159@163.com/ - The patch subject and commit message were modified. Changes since v2~v3: https://lore.kernel.org/linux-pci/20250308133903.322216-1-18255117159@163.com/ https://lore.kernel.org/linux-pci/20250321040358.360755-4-18255117159@163.com/ - Introduce generic capability search functions Changes since v1: https://lore.kernel.org/linux-pci/20250123070935.1810110-1-18255117159@163.com - Added calling the new API in PCI-Cadence ep.c. - Add a commit message reason for adding the API. --- drivers/pci/controller/cadence/pcie-cadence.c | 25 +++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 3 +++ 2 files changed, 28 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c index 204e045aed8c..329dab4ff813 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -8,6 +8,31 @@ #include "pcie-cadence.h" +static u32 cdns_pcie_read_cfg(void *priv, int where, int size) +{ + struct cdns_pcie *pcie = priv; + u32 val; + + if (size == 4) + val = readl(pcie->reg_base + where); + else if (size == 2) + val = readw(pcie->reg_base + where); + else if (size == 1) + val = readb(pcie->reg_base + where); + + return val; +} + +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap) +{ + return pci_host_bridge_find_capability(pcie, cdns_pcie_read_cfg, cap); +} + +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap) +{ + return pci_host_bridge_find_ext_capability(pcie, cdns_pcie_read_cfg, cap); +} + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) { u32 delay = 0x3; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index f5eeff834ec1..6f4981fccb94 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -557,6 +557,9 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) } #endif +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, From patchwork Fri Mar 21 16:38:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14025758 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.5]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A5E461EBA1E; Fri, 21 Mar 2025 16:38:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.5 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742575115; cv=none; b=t/hgvn5Rgfm6UW2wAIGBVu+YK+QNtsv+2q5KREwa/SLB0nijX2S9AuXfgCrPKysDBB4d2S7GzvuxwjN08OgdyDD6IDq8arl2+UMsXhwNBFq2Ay+yG4IHb3SVWTap76XfPzbm11kLi45DXH2pYHO1VWEq11iWN7RU3oR7f6W8i78= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742575115; c=relaxed/simple; bh=JR7S2MATXfTvx5Wz5SjALIQV6FkE1ItKtQhPH4ZewVY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XkEEod3rbox05IjnGixxU78sBYmEp6Zf3zsZPCDI/Sf578tvmCjVCXdXj/2CWHwqXNmKARGbYm67QRklhrUxmOMda2V7CUw8My+JwDyN7ssBQvQKr2uWybclghAA4lghmDokGtHqullV5Nk88t0nA9//LojXlyKfeb8kXUFfRPU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=BR3nkK7k; arc=none smtp.client-ip=220.197.31.5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="BR3nkK7k" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=E9xEI IzUtkwTOd4IZJeKT0N33skdMdQSQIBmezuP4jU=; b=BR3nkK7krfQK9WDHPEd/J HS3abq6LlhO7n4BOB/ui5RsJgNQwW1TaQ9r3ryr2JxJr/JKNBzGKDykcnnPtDum9 YuxcioiJQzAL5Ptlzs45uklinyKBECeoVcr9hUi8JlyN+LOMEhparpicj9Rw9gDq QnD/X6IKHtDPABQaKeKnqo= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-0 (Coremail) with SMTP id _____wC30e7sld1nnmPrAw--.48109S6; Sat, 22 Mar 2025 00:38:07 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v5 4/4] PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode. Date: Sat, 22 Mar 2025 00:38:03 +0800 Message-Id: <20250321163803.391056-5-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250321163803.391056-1-18255117159@163.com> References: <20250321163803.391056-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: _____wC30e7sld1nnmPrAw--.48109S6 X-Coremail-Antispam: 1Uf129KBjvJXoW3JF1xAFy3Jw43GF17ur18AFb_yoWxAw47pF Z8ua4SkF40qrW7uFsrAa15ZrnxtFnIv347Aa92kw1fuF129FyUGFyIva43KF1akrs7uF17 XrWDtrsa9a13trUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pNsjUsUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhsXo2fdjwDO-AAEsW The PCIe capability/extended capability offsets are not guaranteed to be the same across all SoCs integrating the Cadence PCIe IP. Hence, use the cdns_pcie_find_{ext}_capability() APIs for finding them. This avoids hardcoding the offsets in the driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v4: https://lore.kernel.org/linux-pci/20250321101710.371480-5-18255117159@163.com/ - The patch subject and commit message were modified. --- .../pci/controller/cadence/pcie-cadence-ep.c | 40 +++++++++++-------- drivers/pci/controller/cadence/pcie-cadence.h | 5 --- 2 files changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index e0cc4560dfde..aea53ddcaf9b 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -19,12 +19,13 @@ static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) { - u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; u32 first_vf_offset, stride; + u16 cap; if (vfn == 0) return fn; + cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); fn = fn + first_vf_offset + ((vfn - 1) * stride); @@ -36,10 +37,11 @@ static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, struct pci_epf_header *hdr) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); - u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; struct cdns_pcie *pcie = &ep->pcie; u32 reg; + u16 cap; + cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); if (vfn > 1) { dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); return -EINVAL; @@ -224,9 +226,10 @@ static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* @@ -246,9 +249,10 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* Validate that the MSI feature is actually enabled. */ @@ -269,9 +273,10 @@ static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); func_no = cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); reg = cap + PCI_MSIX_FLAGS; @@ -290,9 +295,10 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); reg = cap + PCI_MSIX_FLAGS; @@ -379,11 +385,11 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, u8 interrupt_num) { struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme, data, data_mask; - u8 msi_count; u64 pci_addr, pci_addr_mask = 0xff; + u8 msi_count, cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -431,14 +437,14 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, u32 *msi_addr_offset) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; struct cdns_pcie *pcie = &ep->pcie; u64 pci_addr, pci_addr_mask = 0xff; u16 flags, mme, data, data_mask; - u8 msi_count; + u8 msi_count, cap; int ret; int i; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -481,16 +487,16 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, u16 interrupt_num) { - u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 tbl_offset, msg_data, reg; struct cdns_pcie *pcie = &ep->pcie; struct pci_epf_msix_tbl *msix_tbl; struct cdns_pcie_epf *epf; u64 pci_addr_mask = 0xff; u64 msg_addr; + u8 bir, cap; u16 flags; - u8 bir; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); epf = &ep->epf[fn]; if (vfn > 0) epf = &epf->epf[vfn - 1]; @@ -564,7 +570,9 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) int max_epfs = sizeof(epc->function_num_map) * 8; int ret, epf, last_fn; u32 reg, value; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP); /* * BIT(0) is hardwired to 1, hence function 0 is always enabled * and can't be disabled anyway. @@ -588,12 +596,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) continue; value = cdns_pcie_ep_fn_readl(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP); + cap + PCI_EXP_DEVCAP); value &= ~PCI_EXP_DEVCAP_FLR; - cdns_pcie_ep_fn_writel(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP, value); + cdns_pcie_ep_fn_writel(pcie, epf, cap + PCI_EXP_DEVCAP, + value); } } diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 6f4981fccb94..d0fcf1b3549c 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -125,11 +125,6 @@ */ #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) -#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 -#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 -#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 - /* * Endpoint PF Registers */