From patchwork Sun Mar 23 16:48:48 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14026543 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F25501519BD; Sun, 23 Mar 2025 16:50:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742748625; cv=none; b=jGJy8J6G1qs2uxjmg6tTcTvqADWuwgQd16Yn5ODbsHOJF2yoPQ+wOxmLS5zspDmgwpy+mzHenxu4sG7kA3zCA1b2jbP+fuSQ2+znzCbdSA4KrOP7w9hNiu+i+WaChWvI4l3991RPFWlpkwA1GCITYu++BzCfKJscJNaC0qQtl38= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742748625; c=relaxed/simple; bh=jMT+KAGX2sw6R2Dh92dbrmSzCyTEYmf9uIPdgFLH+Iw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=V5IX/MsJNAR00mbtX5Pp1b2UTGECd8ciEvkq5tG43ak7nH18gaVQd/pfnb6K92+L4CGsRKF4DhPHgjuKNW1LAMsZn2Qgpi0xV2ESbk/TxkoeUHgNtgUUfVY9TMpNdVDoM83EbrPtuQkAwGa8khxqcndiBwXYOkWXPNZowu1u/o0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=pMjjEGGd; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="pMjjEGGd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=mYrXD O+0xCOAQ8ThlCzCgpLaD9/qD8lHOs3V5CD2quM=; b=pMjjEGGdR7j4w6mGE/gko JpsGfhkvZwNPwu6nSm+ZoLpeULBpSDxK/DWGpmoVzz1R9xTT7Tv7HxkDRCDuQPJj gdcu4gnHKFbKR2fuT2sidmc+HSQfd34xVb5f4lE8tXuizoEdfTJcfJFyDRHs1Qnw 19cCp//GncXi0zHOFTVVvg= Received: from localhost.localdomain (unknown []) by gzsmtp2 (Coremail) with SMTP id PSgvCgDXX3qlO+Bnk_g8AA--.12082S3; Mon, 24 Mar 2025 00:49:42 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v6 1/5] PCI: Introduce generic capability search functions Date: Mon, 24 Mar 2025 00:48:48 +0800 Message-Id: <20250323164852.430546-2-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250323164852.430546-1-18255117159@163.com> References: <20250323164852.430546-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: PSgvCgDXX3qlO+Bnk_g8AA--.12082S3 X-Coremail-Antispam: 1Uf129KBjvJXoW3AF45JFyDAw15CFy8CF43Awb_yoWxCry7pF ZYv347CF48JF4avw4qv3Wjka43XanrJryUG395GwnxZF47ua1Uu3sFka4rtF1UAr47XF15 JFW5t3ZYkr1DJ3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zE_OzhUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWwwZo2fgMcLw0gAAs7 Existing controller drivers (e.g., DWC, custom out-of-tree drivers) duplicate logic for scanning PCI capability lists. This creates maintenance burdens and risks inconsistencies. To resolve this: Add pci_host_bridge_find_*capability() in pci-host-helpers.c, accepting controller-specific read functions and device data as parameters. This approach: - Centralizes critical PCI capability scanning logic - Allows flexible adaptation to varied hardware access methods - Reduces future maintenance overhead - Aligns with kernel code reuse best practices Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-2-18255117159@163.com - If you put the helpers in drivers/pci/pci.c, they unnecessarily enlarge the kernel's .text section even if it's known already at compile time that they're never going to be used (e.g. on x86). - Move the API for find capabilitys to a new file called pci-host-helpers.c. Changes since v4: https://lore.kernel.org/linux-pci/20250321101710.371480-2-18255117159@163.com - Resolved [v4 1/4] compilation warning. - The patch commit message were modified. --- drivers/pci/controller/Kconfig | 17 ++++ drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pci-host-helpers.c | 98 +++++++++++++++++++++++ drivers/pci/pci.h | 7 ++ 4 files changed, 123 insertions(+) create mode 100644 drivers/pci/controller/pci-host-helpers.c diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 9800b7681054..0020a892a55b 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -132,6 +132,23 @@ config PCI_HOST_GENERIC Say Y here if you want to support a simple generic PCI host controller, such as the one emulated by kvmtool. +config PCI_HOST_HELPERS + bool + prompt "PCI Host Controller Helper Functions" if EXPERT + help + This provides common infrastructure for PCI host controller drivers to + handle PCI capability scanning and other shared operations. The helper + functions eliminate code duplication across controller drivers. + + These functions are used by PCI controller drivers that need to scan + PCI capabilities using controller-specific access methods (e.g. when + the controller is behind a non-standard configuration space). + + If you are using any PCI host controller drivers that require these + helpers (such as DesignWare, Cadence, etc), this will be + automatically selected. Say N unless you are developing a custom PCI + host controller driver. + config PCIE_HISI_ERR depends on ACPI_APEI_GHES && (ARM64 || COMPILE_TEST) bool "HiSilicon HIP PCIe controller error handling driver" diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index 038ccbd9e3ba..e80091eb7597 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar.o pcie-rcar-host.o obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o obj-$(CONFIG_PCI_HOST_COMMON) += pci-host-common.o obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o +obj-$(CONFIG_PCI_HOST_HELPERS) += pci-host-helpers.o obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o diff --git a/drivers/pci/controller/pci-host-helpers.c b/drivers/pci/controller/pci-host-helpers.c new file mode 100644 index 000000000000..cd261a281c60 --- /dev/null +++ b/drivers/pci/controller/pci-host-helpers.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCI Host Controller Helper Functions + * + * Copyright (C) 2025 Hans Zhang + * + * Author: Hans Zhang <18255117159@163.com> + */ + +#include + +#include "../pci.h" + +/* + * These interfaces resemble the pci_find_*capability() interfaces, but these + * are for configuring host controllers, which are bridges *to* PCI devices but + * are not PCI devices themselves. + */ +static u8 __pci_host_bridge_find_next_cap(void *priv, + pci_host_bridge_read_cfg read_cfg, + u8 cap_ptr, u8 cap) +{ + u8 cap_id, next_cap_ptr; + u16 reg; + + if (!cap_ptr) + return 0; + + reg = read_cfg(priv, cap_ptr, 2); + cap_id = (reg & 0x00ff); + + if (cap_id > PCI_CAP_ID_MAX) + return 0; + + if (cap_id == cap) + return cap_ptr; + + next_cap_ptr = (reg & 0xff00) >> 8; + return __pci_host_bridge_find_next_cap(priv, read_cfg, next_cap_ptr, + cap); +} + +u8 pci_host_bridge_find_capability(void *priv, + pci_host_bridge_read_cfg read_cfg, u8 cap) +{ + u8 next_cap_ptr; + u16 reg; + + reg = read_cfg(priv, PCI_CAPABILITY_LIST, 2); + next_cap_ptr = (reg & 0x00ff); + + return __pci_host_bridge_find_next_cap(priv, read_cfg, next_cap_ptr, + cap); +} +EXPORT_SYMBOL_GPL(pci_host_bridge_find_capability); + +static u16 pci_host_bridge_find_next_ext_capability( + void *priv, pci_host_bridge_read_cfg read_cfg, u16 start, u8 cap) +{ + u32 header; + int ttl; + int pos = PCI_CFG_SPACE_SIZE; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + if (start) + pos = start; + + header = read_cfg(priv, pos, 4); + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + return 0; + + while (ttl-- > 0) { + if (PCI_EXT_CAP_ID(header) == cap && pos != start) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (pos < PCI_CFG_SPACE_SIZE) + break; + + header = read_cfg(priv, pos, 4); + } + + return 0; +} + +u16 pci_host_bridge_find_ext_capability(void *priv, + pci_host_bridge_read_cfg read_cfg, + u8 cap) +{ + return pci_host_bridge_find_next_ext_capability(priv, read_cfg, 0, cap); +} +EXPORT_SYMBOL_GPL(pci_host_bridge_find_ext_capability); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 01e51db8d285..8d1c919cbfef 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1034,4 +1034,11 @@ void pcim_release_region(struct pci_dev *pdev, int bar); (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ PCI_CONF1_EXT_REG(reg)) +typedef u32 (*pci_host_bridge_read_cfg)(void *priv, int where, int size); +u8 pci_host_bridge_find_capability(void *priv, + pci_host_bridge_read_cfg read_cfg, u8 cap); +u16 pci_host_bridge_find_ext_capability(void *priv, + pci_host_bridge_read_cfg read_cfg, + u8 cap); + #endif /* DRIVERS_PCI_H */ From patchwork Sun Mar 23 16:48:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14026541 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4E24D14A095; Sun, 23 Mar 2025 16:50:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.210.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742748622; cv=none; b=d481ZO76c9Rn9cHNtOSu9QefHBp+0HvnYA/9GBDdMilw/rxn4V4Vk994mZVRnr/lAvsnwELEd+XBx9iragC5e0/m9gKPexWmgz5S3riosaC52ab1q02h94QSlWkJoFLeUkYQwbozItOvi+NDznlrI17s3J1ASAHbYW7UOsKfpVA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742748622; c=relaxed/simple; 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b=F0bpFi23PsAPS0hU+wHRa AkllcPjwEAM/CW05LKCx790wBFNvkAvPkqYwD2nKG7zgWNi27irO+UhItXm/CGnr a2ZZAchZMRBqDRO4DDwJJBhqrsgyQpeBf9I+niqZvD58YfC3mvJUkxSpmeTJgj+4 Z+u/yhuKpKD4PvkcPkcBy8= Received: from localhost.localdomain (unknown []) by gzsmtp2 (Coremail) with SMTP id PSgvCgDXX3qlO+Bnk_g8AA--.12082S4; Mon, 24 Mar 2025 00:49:43 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v6 2/5] PCI: dwc: Use common PCI host bridge APIs for finding the capabilities Date: Mon, 24 Mar 2025 00:48:49 +0800 Message-Id: <20250323164852.430546-3-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250323164852.430546-1-18255117159@163.com> References: <20250323164852.430546-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: PSgvCgDXX3qlO+Bnk_g8AA--.12082S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxZF45JrWfKr4UKw45JrWDArb_yoW5uw4kpa yrJ3WakF1rtF4Yqw4DA3WFkF15AF9xAFW7Aa97GwnavF17CrWUu340yaySqF1fArZFgF13 Kr48ta4rCr18JFDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zi038nUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxkZo2fgMcLw5QAAsZ Since the PCI core is now exposing generic APIs for the host bridges to search for the PCIe capabilities, make use of them in the DWC driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-3-18255117159@163.com/ - Kconfig add "select PCI_HOST_HELPERS" --- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-designware.c | 71 ++------------------ 2 files changed, 6 insertions(+), 66 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index b6d6778b0698..c71b3ad44f3e 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -5,6 +5,7 @@ menu "DesignWare-based PCIe controllers" config PCIE_DW bool + select PCI_HOST_HELPERS config PCIE_DW_HOST bool diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 145e7f579072..0329f233cf11 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -203,83 +203,22 @@ void dw_pcie_version_detect(struct dw_pcie *pci) pci->type = ver; } -/* - * These interfaces resemble the pci_find_*capability() interfaces, but these - * are for configuring host controllers, which are bridges *to* PCI devices but - * are not PCI devices themselves. - */ -static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, - u8 cap) +static u32 dwc_pcie_read_cfg(void *priv, int where, int size) { - u8 cap_id, next_cap_ptr; - u16 reg; - - if (!cap_ptr) - return 0; - - reg = dw_pcie_readw_dbi(pci, cap_ptr); - cap_id = (reg & 0x00ff); - - if (cap_id > PCI_CAP_ID_MAX) - return 0; + struct dw_pcie *pci = priv; - if (cap_id == cap) - return cap_ptr; - - next_cap_ptr = (reg & 0xff00) >> 8; - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return dw_pcie_read_dbi(pci, where, size); } u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) { - u8 next_cap_ptr; - u16 reg; - - reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); - next_cap_ptr = (reg & 0x00ff); - - return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); + return pci_host_bridge_find_capability(pci, dwc_pcie_read_cfg, cap); } EXPORT_SYMBOL_GPL(dw_pcie_find_capability); -static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start, - u8 cap) -{ - u32 header; - int ttl; - int pos = PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (start) - pos = start; - - header = dw_pcie_readl_dbi(pci, pos); - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header == 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) == cap && pos != start) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - header = dw_pcie_readl_dbi(pci, pos); - } - - return 0; -} - u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap) { - return dw_pcie_find_next_ext_capability(pci, 0, cap); + return pci_host_bridge_find_ext_capability(pci, dwc_pcie_read_cfg, cap); } EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); From patchwork Sun Mar 23 16:48:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14026542 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.3]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F2C411519BE; Sun, 23 Mar 2025 16:50:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.3 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742748625; cv=none; b=O7wN1ii393Z6uI1xN2gOYWDlfhcaHs1MqnDKEGv/BmI7s0xitzZ+fU4L+VLmK5EdMfbFJv0V2D3i7aERyQgT8Vob95idjGTc0YZejnKJE9R1dyA2iFPJObJeeyL4e2cUaLnQnTegMsA461EWHJ/R+1cmvMKQIKtby1P0dA+zUgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742748625; c=relaxed/simple; bh=sMpGyV6p8pOURoqAQl1m8+lvi69TfLNxdVcEY8ooH+E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kU50JORLw4QiHAV31gJynerwUjqTnlhbmxaafuhCKw2LvNzHo7DxJXC3BpJbjx3arroQb5qGDBqVf3NNVNMt1CXssRG5XONruYphokmArmb/FX6pfkGcFfbhbQDeAlDmPj3asQxmcGYANdXO7MxwdtiKUC8GRyuf+C3SzsCQapA= ARC-Authentication-Results: i=1; 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Mon, 24 Mar 2025 00:49:44 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v6 3/5] PCI: cadence: Use common PCI host bridge APIs for finding the capabilities Date: Mon, 24 Mar 2025 00:48:50 +0800 Message-Id: <20250323164852.430546-4-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250323164852.430546-1-18255117159@163.com> References: <20250323164852.430546-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: PSgvCgDXX3qlO+Bnk_g8AA--.12082S5 X-Coremail-Antispam: 1Uf129KBjvJXoWxWr1xKF4kur1UWr43CF17Jrb_yoW5XFyUpF yUGFyfCF1rJFW3uan3Za4UXF15J3Zay347t392k34fZF17CryUGFnFgFyftFZxKrsrWr17 XryDtas7Kr1rtrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zRvtC-UUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiWxkZo2fgMcLw5QABsY Since the PCI core is now exposing generic APIs for the host bridges to search for the PCIe capabilities, make use of them in the CDNS driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v5: https://lore.kernel.org/linux-pci/20250321163803.391056-4-18255117159@163.com - Kconfig add "select PCI_HOST_HELPERS" --- drivers/pci/controller/cadence/Kconfig | 1 + drivers/pci/controller/cadence/pcie-cadence.c | 25 +++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 3 +++ 3 files changed, 29 insertions(+) diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig index 8a0044bb3989..0a4f245bbeb0 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -5,6 +5,7 @@ menu "Cadence-based PCIe controllers" config PCIE_CADENCE bool + select PCI_HOST_HELPERS config PCIE_CADENCE_HOST bool diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c index 204e045aed8c..329dab4ff813 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -8,6 +8,31 @@ #include "pcie-cadence.h" +static u32 cdns_pcie_read_cfg(void *priv, int where, int size) +{ + struct cdns_pcie *pcie = priv; + u32 val; + + if (size == 4) + val = readl(pcie->reg_base + where); + else if (size == 2) + val = readw(pcie->reg_base + where); + else if (size == 1) + val = readb(pcie->reg_base + where); + + return val; +} + +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap) +{ + return pci_host_bridge_find_capability(pcie, cdns_pcie_read_cfg, cap); +} + +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap) +{ + return pci_host_bridge_find_ext_capability(pcie, cdns_pcie_read_cfg, cap); +} + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) { u32 delay = 0x3; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index f5eeff834ec1..6f4981fccb94 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -557,6 +557,9 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) } #endif +u8 cdns_pcie_find_capability(struct cdns_pcie *pcie, u8 cap); +u16 cdns_pcie_find_ext_capability(struct cdns_pcie *pcie, u8 cap); + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, From patchwork Sun Mar 23 16:48:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14026539 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9ECBF35893; Sun, 23 Mar 2025 16:50:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742748616; cv=none; b=P7KOXsCpCUwXWq3ieqksGiFHgPFKARcbaeJea6rSapFOoUimxFf0eHEMz8gPxPPwWzT1HZhFSGxvPdIFZZSzB2XzmGoCllM2O1UjzHx7b3jpaNSA2PvLh8tL51lqzunWAVN9WextKtvNtEDVxbT/HBrzEeCtoHz4vgca1hfH+V8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742748616; c=relaxed/simple; bh=TvECmO0Fu+bKnEU8yE8XoG98LRyBJeTuoD5bCBlUYxk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=J0BFbDu6+d0L7L3pRwfDnXY3xO/3gTJ8Cjeq9mZg6Z/oP58JyrsydF/WnINR7/0/ks7GjdZ/V0FXexh/PbyDRoJPZlgefB3L0BJHwJAs6vXKD/vC+knGQVDSGLamz4wR9p7nrZ4WBjq1OsjkGSH3kmg3l7NcJ279yNE6TtMcjtE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=fjACqNMs; arc=none smtp.client-ip=220.197.31.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="fjACqNMs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=GOzL/ qOVyj6ngzIO9V5yftfrKL+s+MMXoniPsjo+Pfw=; b=fjACqNMsqBgpLy/bpMgKE W2FF3E1OKRtJvnvwWQThbwR16Mj6Y5mvgZneYD3WdY7QNC6qQm67S3g/tLduF0ZE mfU1I0HYnsKe6O2DJdxTQ5e5/mc8W1b9F494SR+Ea0C07Tw6BHja1hl9uOLExzUs 53TQaYFq1ipoLQcg+8vFsE= Received: from localhost.localdomain (unknown []) by gzsmtp2 (Coremail) with SMTP id PSgvCgDXX3qlO+Bnk_g8AA--.12082S6; Mon, 24 Mar 2025 00:49:45 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v6 4/5] PCI: cadence: Use cdns_pcie_find_*capability to avoid hardcode. Date: Mon, 24 Mar 2025 00:48:51 +0800 Message-Id: <20250323164852.430546-5-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250323164852.430546-1-18255117159@163.com> References: <20250323164852.430546-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: PSgvCgDXX3qlO+Bnk_g8AA--.12082S6 X-Coremail-Antispam: 1Uf129KBjvJXoW3JF1xAFy3Jw43GF17ur18AFb_yoWxCr47pF W5ua4SkF40qrW7uFsrAa15ZrnxtFnIv347Aa92kw1fuF129FyUGFyIva43KF1akrs7uF17 XrWDtrsa9a13trUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pNsjUsUUUUU= X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/xtbBDwIZo2fgMeLr7wAAsn The PCIe capability/extended capability offsets are not guaranteed to be the same across all SoCs integrating the Cadence PCIe IP. Hence, use the cdns_pcie_find_{ext}_capability() APIs for finding them. This avoids hardcoding the offsets in the driver. Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v5: - None Changes since v4: https://lore.kernel.org/linux-pci/20250321101710.371480-5-18255117159@163.com/ - The patch subject and commit message were modified. --- .../pci/controller/cadence/pcie-cadence-ep.c | 40 +++++++++++-------- drivers/pci/controller/cadence/pcie-cadence.h | 5 --- 2 files changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index e0cc4560dfde..aea53ddcaf9b 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -19,12 +19,13 @@ static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) { - u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; u32 first_vf_offset, stride; + u16 cap; if (vfn == 0) return fn; + cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); fn = fn + first_vf_offset + ((vfn - 1) * stride); @@ -36,10 +37,11 @@ static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, struct pci_epf_header *hdr) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); - u32 cap = CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; struct cdns_pcie *pcie = &ep->pcie; u32 reg; + u16 cap; + cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SRIOV); if (vfn > 1) { dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); return -EINVAL; @@ -224,9 +226,10 @@ static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* @@ -246,9 +249,10 @@ static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* Validate that the MSI feature is actually enabled. */ @@ -269,9 +273,10 @@ static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); func_no = cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); reg = cap + PCI_MSIX_FLAGS; @@ -290,9 +295,10 @@ static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 val, reg; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); reg = cap + PCI_MSIX_FLAGS; @@ -379,11 +385,11 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, u8 interrupt_num) { struct cdns_pcie *pcie = &ep->pcie; - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; u16 flags, mme, data, data_mask; - u8 msi_count; u64 pci_addr, pci_addr_mask = 0xff; + u8 msi_count, cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -431,14 +437,14 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, u32 *msi_addr_offset) { struct cdns_pcie_ep *ep = epc_get_drvdata(epc); - u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; struct cdns_pcie *pcie = &ep->pcie; u64 pci_addr, pci_addr_mask = 0xff; u16 flags, mme, data, data_mask; - u8 msi_count; + u8 msi_count, cap; int ret; int i; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSI); fn = cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); /* Check whether the MSI feature has been enabled by the PCI host. */ @@ -481,16 +487,16 @@ static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 vfn, u16 interrupt_num) { - u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; u32 tbl_offset, msg_data, reg; struct cdns_pcie *pcie = &ep->pcie; struct pci_epf_msix_tbl *msix_tbl; struct cdns_pcie_epf *epf; u64 pci_addr_mask = 0xff; u64 msg_addr; + u8 bir, cap; u16 flags; - u8 bir; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_MSIX); epf = &ep->epf[fn]; if (vfn > 0) epf = &epf->epf[vfn - 1]; @@ -564,7 +570,9 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) int max_epfs = sizeof(epc->function_num_map) * 8; int ret, epf, last_fn; u32 reg, value; + u8 cap; + cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP); /* * BIT(0) is hardwired to 1, hence function 0 is always enabled * and can't be disabled anyway. @@ -588,12 +596,10 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) continue; value = cdns_pcie_ep_fn_readl(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP); + cap + PCI_EXP_DEVCAP); value &= ~PCI_EXP_DEVCAP_FLR; - cdns_pcie_ep_fn_writel(pcie, epf, - CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + - PCI_EXP_DEVCAP, value); + cdns_pcie_ep_fn_writel(pcie, epf, cap + PCI_EXP_DEVCAP, + value); } } diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 6f4981fccb94..d0fcf1b3549c 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -125,11 +125,6 @@ */ #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) -#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 -#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 -#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 - /* * Endpoint PF Registers */ From patchwork Sun Mar 23 16:48:52 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Zhang <18255117159@163.com> X-Patchwork-Id: 14026544 X-Patchwork-Delegate: kw@linux.com Received: from m16.mail.163.com (m16.mail.163.com [117.135.210.4]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D85C5156C76; Sun, 23 Mar 2025 16:50:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="p6k6f5RQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=5EAGM V7SwM4hXg2KpoIhfhVyUycJB3dJKNluHvxyOBg=; b=p6k6f5RQFqtYWW3fY05sU LbmiJosZu0BhPCezKQSW49HvT4agmMtTvi1aSLFDHZuzfXsIiGu+kdK+HT/fniez c+0RjZ+Yp4/UkSE5h1PzjI0qNxCTj37v1rFyFYC5reGmcLPgyV9rYM0p84++o1e1 xxaG6QpWnRaBMvdJfvI8nQ= Received: from localhost.localdomain (unknown []) by gzsmtp2 (Coremail) with SMTP id PSgvCgDXX3qlO+Bnk_g8AA--.12082S7; Mon, 24 Mar 2025 00:49:46 +0800 (CST) From: Hans Zhang <18255117159@163.com> To: lpieralisi@kernel.org Cc: kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang <18255117159@163.com> Subject: [v6 5/5] MAINTAINERS: Add entry for PCI host controller helpers Date: Mon, 24 Mar 2025 00:48:52 +0800 Message-Id: <20250323164852.430546-6-18255117159@163.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250323164852.430546-1-18255117159@163.com> References: <20250323164852.430546-1-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-CM-TRANSID: PSgvCgDXX3qlO+Bnk_g8AA--.12082S7 X-Coremail-Antispam: 1Uf129KBjvdXoWruF4xur48tFWUKw1fKF17KFg_yoWDJFc_Cr 18GFWxZr4UGFyFkay0kFZ2vryayw4jqrn3uas7twsrAayUXFy5Jr1ktrWq9w1UZr4fGrWa qF98tF1xCr17CjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7sR_lApUUUUUU== X-CM-SenderInfo: rpryjkyvrrlimvzbiqqrwthudrp/1tbiOhgZo2fgNS+dHwAAsH Add maintenance entry for the newly introduced PCI host controller helper functions. These functions provide common infrastructure for capability scanning and other shared operations across PCI host controller drivers. Signed-off-by: Hans Zhang <18255117159@163.com> --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 00e94bec401e..9b3236704b83 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18119,6 +18119,12 @@ S: Maintained F: Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml F: drivers/pci/controller/pci-ixp4xx.c +PCI DRIVER FOR HELPER FUNCTIONS +M: Hans Zhang <18255117159@163.com> +L: linux-pci@vger.kernel.org +S: Maintained +F: drivers/pci/controller/pci-host-helpers.c + PCI DRIVER FOR INTEL VOLUME MANAGEMENT DEVICE (VMD) M: Nirmal Patel R: Jonathan Derrick