From patchwork Tue Mar 25 15:55:07 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 14029177 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD27B25332E; Tue, 25 Mar 2025 15:56:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742918196; cv=none; b=Jo5PF6/z8YhlSFG++E5ympMZT73SbRpbUs/s8RFI+dTaVFphFKuGwQEV3aHkESeCykEIsHSnL5OIYJMZuyam6R7pqzT1tW1dgkZION5GCLd8KizmFy5sn5ABvofCiSJk5M74FtGdnmCdi4Iodg4pNeLHh88iR3gV4S+nBipPCx0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742918196; c=relaxed/simple; bh=njhp2XtVb4PhtB0KA2dZs1VqgKACFt3lVxVn3QeR+2o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kDwkltri/EN5cslF7LZgsncfvGkhRzQB9+pA2APz/eSK1qgAj1CHjAnZA+Esf/ZrRgLai8xFuq57/LPyGHkRmtDFHiBAvHkLgewszL16fh6b9OYbpUYRR3mngoCzPj84oQN0d5W1d9DJNw94fb6edBlxy3uvFXGXkEo7Iu6WCbA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=J70eifHM; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="J70eifHM" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1742918194; x=1774454194; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=njhp2XtVb4PhtB0KA2dZs1VqgKACFt3lVxVn3QeR+2o=; b=J70eifHM+wtALNmE/TrY7nmKr6ZQXrB/eMiMDP8fmPNvJlRFiOBjeV1l Bv2bgUDhlkC5B6cHMY2Ea9lGnqj+QAdxD75Z88XIidK1PuuC9+5Ou5MjH oNK64jVvEGzWQwNyziwmutBng4XYeSXmjTy8rzyNC4LeK2kvHwOZ+JH7H Oz2FRX42+qMuAfaxNZqp/WnR7XZglLaBuEqnO6Ymyd1tPE7fz3NwFyJj2 KCD5odw4gvhpIFArxKqARFYvGp0bWoL6dmp6SvTNipcL3Y3GXNGNQUgfm lnxNKHRilA2QHlWDdLj7aItIaHc4LGkjT0oBw6jZzVxcV+ncZ+XNZJlHU Q==; X-CSE-ConnectionGUID: 5ZRRXf5LQVCIU2dRAgtdWw== X-CSE-MsgGUID: do4csKX9TtyoN10bzub/Vw== X-IronPort-AV: E=Sophos;i="6.14,275,1736838000"; d="scan'208";a="40152229" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 25 Mar 2025 08:55:24 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 25 Mar 2025 08:54:53 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 25 Mar 2025 08:54:53 -0700 From: To: , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v2 1/4] clk: at91: sckc: Fix parent_data struct for slow osc Date: Tue, 25 Mar 2025 08:55:07 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner The slow xtal is not described correctly as a parent, the driver looks for a "slow_xtal" string which is incorrect and will not work with the new formating of xtals. To avoid this and keep this driver backwards compatible the parent_data.fw_name is replaced with parent_data.name and the original parent_data.name is replaced with parent_data.index. Using the index is safe due to the driver requiring only 1 xtal. Fixes: 8aa1db9ccee0e ("clk: at91: sckc: switch to parent_data/parent_hw") Signed-off-by: Ryan Wanner --- drivers/clk/at91/sckc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c index 021d1b412af4..952a805b6f7e 100644 --- a/drivers/clk/at91/sckc.c +++ b/drivers/clk/at91/sckc.c @@ -374,7 +374,7 @@ static void __init at91sam9x5_sckc_register(struct device_node *np, const char *xtal_name; struct clk_hw *slow_rc, *slow_osc, *slowck; static struct clk_parent_data parent_data = { - .name = "slow_xtal", + .index = 0, }; const struct clk_hw *parent_hws[2]; bool bypass; @@ -407,7 +407,7 @@ static void __init at91sam9x5_sckc_register(struct device_node *np, if (!xtal_name) goto unregister_slow_rc; - parent_data.fw_name = xtal_name; + parent_data.name = xtal_name; slow_osc = at91_clk_register_slow_osc(regbase, "slow_osc", &parent_data, 1200000, bypass, bits); @@ -476,7 +476,7 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np) const char *xtal_name; const struct clk_hw *parent_hws[2]; static struct clk_parent_data parent_data = { - .name = "slow_xtal", + .index = 0, }; bool bypass; int ret; @@ -494,7 +494,7 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np) if (!xtal_name) goto unregister_slow_rc; - parent_data.fw_name = xtal_name; + parent_data.name = xtal_name; bypass = of_property_read_bool(np, "atmel,osc-bypass"); slow_osc = at91_clk_register_slow_osc(regbase, "slow_osc", &parent_data, 5000000, bypass, @@ -592,7 +592,7 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np) const char *xtal_name; const struct clk_hw *parent_hws[2]; static struct clk_parent_data parent_data = { - .name = "slow_xtal", + .index = 0, }; int ret; @@ -609,7 +609,7 @@ static void __init of_sama5d4_sckc_setup(struct device_node *np) xtal_name = of_clk_get_parent_name(np, 0); if (!xtal_name) goto unregister_slow_rc; - parent_data.fw_name = xtal_name; + parent_data.name = xtal_name; osc = kzalloc(sizeof(*osc), GFP_KERNEL); if (!osc) From patchwork Tue Mar 25 15:55:08 2025 Content-Type: text/plain; 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Tue, 25 Mar 2025 08:54:53 -0700 From: To: , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v2 2/4] clk: at91: sama7d65: Add missing clk_hw to parent_data Date: Tue, 25 Mar 2025 08:55:08 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner The main_xtal clk_hw struct is not passed into parent_data.hw causing an issue with main_osc parent. Passing the main_xtal struct into the parent_data struct will ensure the correct parent structure. Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama7d65.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c index a5d40df8b2f2..08306261c9c7 100644 --- a/drivers/clk/at91/sama7d65.c +++ b/drivers/clk/at91/sama7d65.c @@ -1138,6 +1138,7 @@ static void __init sama7d65_pmc_setup(struct device_node *np) parent_data.name = main_xtal_name; parent_data.fw_name = main_xtal_name; + parent_data.hw = main_xtal_hw; main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL, &parent_data, bypass); if (IS_ERR(main_osc_hw)) From patchwork Tue Mar 25 15:55:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 14029179 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E88DE25D1E3; Tue, 25 Mar 2025 15:56:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742918198; cv=none; b=su+/C9lehEeLSgjv8UqSTHiM1Av1GkV2mRwxqOwV6p8LOZT6wjVRcK/FRXEfG6GxqxJP4Q/0eYECYgNar+3gmVJc1Q8R796SVWV7RB7N2TVpYo1q1U68cr6qZzC0yYAQJQo7GwFFHGYpc0i6G6PHfG/QPF2g+uwxzulbp0xKPDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742918198; c=relaxed/simple; bh=KTXtnWwkPZ9dd4XF9bTY1ABrcDQk0xQphr+uv8Hqj7A=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NnDrt7GKTTcOfigecKdErYoIOQy+S9cGX22man1ghZSLs6QVkqve1uT+itO7MXJAvLTAEPXV4jDBnNV8eC9905wbn4QZVi6QPzAdVpqqoKRRfnvZhl6Xjw34g0H9EuTo4PypvMNtBGe8bBfv/OHshpXiJjA/O940vqagrF9NQjQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=ELYBToYa; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ELYBToYa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1742918197; x=1774454197; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KTXtnWwkPZ9dd4XF9bTY1ABrcDQk0xQphr+uv8Hqj7A=; b=ELYBToYafEe1x0mm5h8/1czsj2rSQg3RcnzkuKkdFIWBfqIcTot24l1M Jpga4WGZMqrtZpEYJep3AhS3dn4J1kN2eEbjxG28CgmkrTSUomvZrGXk7 /vm4Ab+RSj17aKpXVLwULKp938IriAGJGsaqvkU7PsY9CkTnFXhYJNSml sh5bcB8doGsrqI2xVOH88+AsEhK84BR+ANXo+gSqRzK0d1C1Se9ubT4bM Ax3K4LQFOgHW+RUxDlQrsOpbMBD/OIUAAptt378R+W6Uz0buogm79BfQP kDa+tds3kZpDyGVJfimHX4wOtU+knNoIlXroe7B51i/OMK7Ed7BEITTBW g==; X-CSE-ConnectionGUID: 5ZRRXf5LQVCIU2dRAgtdWw== X-CSE-MsgGUID: J3K9ZU4iQeaA5GTgDrFq0Q== X-IronPort-AV: E=Sophos;i="6.14,275,1736838000"; d="scan'208";a="40152234" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 25 Mar 2025 08:55:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 25 Mar 2025 08:54:54 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 25 Mar 2025 08:54:53 -0700 From: To: , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v2 3/4] clk: at91: sama7g5: Add missing clk_hw to parent_data Date: Tue, 25 Mar 2025 08:55:09 -0700 Message-ID: <690cf499758c10ad5f70df3f0d238b8a7834a971.1742916867.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner The main_xtal clk_hw struct is not passed into parent_data.hw causing an issue with main_osc parent. Passing the main_xtal struct into the parent_data struct will ensure the correct parent structure. Signed-off-by: Ryan Wanner --- drivers/clk/at91/sama7g5.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index 8385badc1c70..ac51d006ba99 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -1017,6 +1017,7 @@ static void __init sama7g5_pmc_setup(struct device_node *np) parent_data.name = main_xtal_name; parent_data.fw_name = main_xtal_name; + parent_data.hw = main_xtal_hw; main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL, &parent_data, bypass); if (IS_ERR(main_osc_hw)) From patchwork Tue Mar 25 15:55:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Wanner X-Patchwork-Id: 14029175 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E24F18A6AB; Tue, 25 Mar 2025 15:55:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742918133; cv=none; b=Rn96fzV65uwe/aibVTaYAtClqTD6pYA0lQa+gwG1vi17SWo2h0rfZkz0A53T+GFoTd761dLAiqGzq+gHNFt4vjFpzOaQ9zp7hpiOt2PqDFvqJthXxNaAAOaczXES8pYf3ss9P99tsHak5zFkSJS+Zdn7r+NLiN2YQmXr4Q3vIFU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742918133; c=relaxed/simple; bh=jfgSiqLCqwkZI4qYAO/dSdiUYlqbnqAIsGKA2fS7izw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sqHgvtj2G+43cEwRMw07bw8SNVKpqESUBcOHL4SRgPj0KKTIpHaq52o1LOxGG/sly0JDvSsJ24OBwQOz/AyxHjEikws6IUEq5BjUCBP1h6Dtufn6A/YSL7W7srCUFsNZEHexMLOV8/2A2WXKL7s4Xp319fU3UHeXUvOo0YX3NIs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=PmxVGHTh; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="PmxVGHTh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1742918131; x=1774454131; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jfgSiqLCqwkZI4qYAO/dSdiUYlqbnqAIsGKA2fS7izw=; b=PmxVGHTh+d5Am8/eFdrEtYTgLwHEr6kGm25vwmL3/drOXVXNjnuQDrOn 69/lX0zfabu5QfXGtxod3xOqiO6Ezg9SphDfV1/Crn8Kkl8WBO+WlXZiM Gyt9PnCSBlwdw+GC56laCfp22cv/7w/ikeK/6fZEH1tJrN6E6vE5+GImv KjGDhLu80MZkAJBtKU7uB7vS5VE/c/7J/gEnlknQTHVb9PYvGSnCLNIKL RBTWuagrSx6fy4uZpqOk3GO1BVPEm9k5Ieai6xv2nVoGRQq62MGK5rlwZ sAPMkOhELzpM0RI8Z6dt/8U1YQXGrzsTKAP71BYrNPt+BCQKZH2XwwKZ6 A==; X-CSE-ConnectionGUID: 5ZRRXf5LQVCIU2dRAgtdWw== X-CSE-MsgGUID: ptw/juAZTZWwDMU9R8w8+g== X-IronPort-AV: E=Sophos;i="6.14,275,1736838000"; d="scan'208";a="40152236" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 25 Mar 2025 08:55:25 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 25 Mar 2025 08:54:54 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 25 Mar 2025 08:54:54 -0700 From: To: , , , , , , CC: , , , , , Ryan Wanner Subject: [PATCH v2 4/4] ARM: dts: microchip: sama7g5: Adjust clock xtal phandle Date: Tue, 25 Mar 2025 08:55:10 -0700 Message-ID: <95c33a95347b098bd32861a59bf6ec658c52f65d.1742916867.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ryan Wanner Adjust clock xtal phandles to match the new xtal phandle formatting. Signed-off-by: Ryan Wanner --- arch/arm/boot/dts/microchip/at91-sama7g5ek.dts | 18 ++++++++---------- arch/arm/boot/dts/microchip/sama7g5.dtsi | 4 ++-- 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts index 2543599013b1..79bf58f8c02e 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7g5ek.dts @@ -35,16 +35,6 @@ aliases { i2c2 = &i2c9; }; - clocks { - slow_xtal { - clock-frequency = <32768>; - }; - - main_xtal { - clock-frequency = <24000000>; - }; - }; - gpio-keys { compatible = "gpio-keys"; @@ -512,6 +502,10 @@ spi11: spi@400 { }; }; +&main_xtal { + clock-frequency = <24000000>; +}; + &gmac0 { #address-cells = <1>; #size-cells = <0>; @@ -917,3 +911,7 @@ &vddout25 { vin-supply = <&vdd_3v3>; status = "okay"; }; + +&slow_xtal { + clock-frequency = <32768>; +}; diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi index 17bcdcf0cf4a..250c9e98a8bb 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -117,12 +117,12 @@ map1 { }; clocks { - slow_xtal: slow_xtal { + slow_xtal: clock-slowxtal { compatible = "fixed-clock"; #clock-cells = <0>; }; - main_xtal: main_xtal { + main_xtal: clock-mainxtal { compatible = "fixed-clock"; #clock-cells = <0>; };