From patchwork Tue Mar 25 22:27:18 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Cavitt, Jonathan" X-Patchwork-Id: 14029587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A0075C36005 for ; Tue, 25 Mar 2025 22:27:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1256610E607; Tue, 25 Mar 2025 22:27:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nBj7ulc8"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 666B210E607; Tue, 25 Mar 2025 22:27:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742941646; x=1774477646; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=c/eFbZe9L+kzlJa6CXBL8Bt/Ptkb1bUh4geX+tEJR2M=; b=nBj7ulc8ehhpcoipTxSpe5E7S/43efdlTCmYFd2rN22YvqI3mO/4Ueok XIZXGGhSqAcPS3CJlTUZT1LF/a5lYHkzYXdUyulO+qrScNVU/hzRTCjLr tuoXycZv2oYqXGTh9uKqk5nttE0NHw7UPTnCLHdHeRX59BJ0at+wOi5Jf DHlITTMmGv6sO+HihVdgD3Mm2/WWd13fXIoLZa6kbvGTVSQGBEGilmQnZ ncJ+sJ/SXiY0TY5/yyhcp9F2cA74BFcR+iHlcngvhIFgoGcDChb9bp8hb b1pcnFrvGWK6blBtgMSzv3QZ3CLoQ9bBTM2MbboAmkcP3tOFLSACl1QmQ Q==; X-CSE-ConnectionGUID: riL/LzHnRI2QYWkwBsDigg== X-CSE-MsgGUID: Jg/W9235S+yIcmdECfDSag== X-IronPort-AV: E=McAfee;i="6700,10204,11384"; a="44369291" X-IronPort-AV: E=Sophos;i="6.14,276,1736841600"; d="scan'208";a="44369291" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2025 15:27:26 -0700 X-CSE-ConnectionGUID: iKDPEljhRnmYV78fPJTd2A== X-CSE-MsgGUID: PUH8UNtEShqC2nIUOlclMw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,276,1736841600"; d="scan'208";a="129561843" Received: from dut4086lnl.fm.intel.com ([10.105.10.68]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2025 15:27:25 -0700 From: Jonathan Cavitt To: intel-xe@lists.freedesktop.org Cc: saurabhg.gupta@intel.com, alex.zuo@intel.com, jonathan.cavitt@intel.com, joonas.lahtinen@linux.intel.com, matthew.brost@intel.com, jianxun.zhang@intel.com, shuicheng.lin@intel.com, dri-devel@lists.freedesktop.org, Michal.Wajdeczko@intel.com, michal.mrozek@intel.com, raag.jadav@intel.com, john.c.harrison@intel.com Subject: [PATCH v13 1/6] drm/xe/xe_hw_engine: Map xe and user engine class in header Date: Tue, 25 Mar 2025 22:27:18 +0000 Message-ID: <20250325222724.93226-2-jonathan.cavitt@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250325222724.93226-1-jonathan.cavitt@intel.com> References: <20250325222724.93226-1-jonathan.cavitt@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Move the helper arrays xe_to_user_engine_class and user_to_xe_engine_class to xe_hw_engine_types.h, making them available to more of the xe kernel. This is done for user_to_xe_engine_class to reduce duplication, and xe_to_user_engine_class can and will be used in more than one place in the future. Signed-off-by: Jonathan Cavitt Suggested-by: John Harrison --- drivers/gpu/drm/xe/xe_hw_engine.c | 24 ++++++++++++++++-------- drivers/gpu/drm/xe/xe_hw_engine_types.h | 5 +++++ drivers/gpu/drm/xe/xe_query.c | 18 +----------------- 3 files changed, 22 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c index 8c05fd30b7df..c742f5953e8b 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine.c +++ b/drivers/gpu/drm/xe/xe_hw_engine.c @@ -272,6 +272,22 @@ static const struct engine_info engine_infos[] = { }, }; +const u16 xe_to_user_engine_class[] = { + [XE_ENGINE_CLASS_RENDER] = DRM_XE_ENGINE_CLASS_RENDER, + [XE_ENGINE_CLASS_COPY] = DRM_XE_ENGINE_CLASS_COPY, + [XE_ENGINE_CLASS_VIDEO_DECODE] = DRM_XE_ENGINE_CLASS_VIDEO_DECODE, + [XE_ENGINE_CLASS_VIDEO_ENHANCE] = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE, + [XE_ENGINE_CLASS_COMPUTE] = DRM_XE_ENGINE_CLASS_COMPUTE, +}; + +const enum xe_engine_class user_to_xe_engine_class[] = { + [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER, + [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY, + [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE, + [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE, + [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE, +}; + static void hw_engine_fini(void *arg) { struct xe_hw_engine *hwe = arg; @@ -1022,14 +1038,6 @@ enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe) return engine_infos[hwe->engine_id].domain; } -static const enum xe_engine_class user_to_xe_engine_class[] = { - [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER, - [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY, - [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE, - [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE, - [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE, -}; - /** * xe_hw_engine_lookup() - Lookup hardware engine for class:instance * @xe: xe device diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h index e4191a7a2c31..b17537a77d6c 100644 --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h @@ -6,6 +6,8 @@ #ifndef _XE_HW_ENGINE_TYPES_H_ #define _XE_HW_ENGINE_TYPES_H_ +#include + #include "xe_force_wake_types.h" #include "xe_lrc_types.h" #include "xe_reg_sr_types.h" @@ -21,6 +23,9 @@ enum xe_engine_class { XE_ENGINE_CLASS_MAX = 6, }; +extern const u16 xe_to_user_engine_class[]; +extern const enum xe_engine_class user_to_xe_engine_class[]; + enum xe_hw_engine_id { XE_HW_ENGINE_RCS0, #define XE_HW_ENGINE_RCS_MASK GENMASK_ULL(XE_HW_ENGINE_RCS0, XE_HW_ENGINE_RCS0) diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c index 5e65830dad25..a85cecfb84d6 100644 --- a/drivers/gpu/drm/xe/xe_query.c +++ b/drivers/gpu/drm/xe/xe_query.c @@ -29,22 +29,6 @@ #include "xe_ttm_vram_mgr.h" #include "xe_wa.h" -static const u16 xe_to_user_engine_class[] = { - [XE_ENGINE_CLASS_RENDER] = DRM_XE_ENGINE_CLASS_RENDER, - [XE_ENGINE_CLASS_COPY] = DRM_XE_ENGINE_CLASS_COPY, - [XE_ENGINE_CLASS_VIDEO_DECODE] = DRM_XE_ENGINE_CLASS_VIDEO_DECODE, - [XE_ENGINE_CLASS_VIDEO_ENHANCE] = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE, - [XE_ENGINE_CLASS_COMPUTE] = DRM_XE_ENGINE_CLASS_COMPUTE, -}; - -static const enum xe_engine_class user_to_xe_engine_class[] = { - [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER, - [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY, - [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE, - [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE, - [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE, -}; - static size_t calc_hw_engine_info_size(struct xe_device *xe) { struct xe_hw_engine *hwe; @@ -148,7 +132,7 @@ query_engine_cycles(struct xe_device *xe, if (!gt) return -EINVAL; - if (eci->engine_class >= ARRAY_SIZE(user_to_xe_engine_class)) + if (eci->engine_class >= XE_ENGINE_CLASS_MAX) return -EINVAL; hwe = xe_gt_hw_engine(gt, user_to_xe_engine_class[eci->engine_class], From patchwork Tue Mar 25 22:27:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Cavitt, Jonathan" X-Patchwork-Id: 14029588 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58DF5C36005 for ; Tue, 25 Mar 2025 22:27:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0D9C610E60B; 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X-CSE-ConnectionGUID: pIOQwo3/RauPgsmu/+oCKg== X-CSE-MsgGUID: bgYtlo0KQlSElCjnjvuobw== X-IronPort-AV: E=McAfee;i="6700,10204,11384"; a="44369292" X-IronPort-AV: E=Sophos;i="6.14,276,1736841600"; d="scan'208";a="44369292" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2025 15:27:26 -0700 X-CSE-ConnectionGUID: 5E8mD+FdSf2WCsOujQ9cVA== X-CSE-MsgGUID: qlbDh7eSSe2XokBwNcqtKg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,276,1736841600"; d="scan'208";a="129561863" Received: from dut4086lnl.fm.intel.com ([10.105.10.68]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2025 15:27:25 -0700 From: Jonathan Cavitt To: intel-xe@lists.freedesktop.org Cc: saurabhg.gupta@intel.com, alex.zuo@intel.com, jonathan.cavitt@intel.com, joonas.lahtinen@linux.intel.com, matthew.brost@intel.com, jianxun.zhang@intel.com, shuicheng.lin@intel.com, dri-devel@lists.freedesktop.org, Michal.Wajdeczko@intel.com, michal.mrozek@intel.com, raag.jadav@intel.com, john.c.harrison@intel.com Subject: [PATCH v13 2/6] drm/xe/xe_gt_pagefault: Disallow writes to read-only VMAs Date: Tue, 25 Mar 2025 22:27:19 +0000 Message-ID: <20250325222724.93226-3-jonathan.cavitt@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250325222724.93226-1-jonathan.cavitt@intel.com> References: <20250325222724.93226-1-jonathan.cavitt@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The page fault handler should reject write/atomic access to read only VMAs. Add code to handle this in handle_pagefault after the VMA lookup. Fixes: 3d420e9fa848 ("drm/xe: Rework GPU page fault handling") Signed-off-by: Jonathan Cavitt Suggested-by: Matthew Brost --- drivers/gpu/drm/xe/xe_gt_pagefault.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c index 9fa11e837dd1..3240890aac07 100644 --- a/drivers/gpu/drm/xe/xe_gt_pagefault.c +++ b/drivers/gpu/drm/xe/xe_gt_pagefault.c @@ -237,6 +237,11 @@ static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf) goto unlock_vm; } + if (xe_vma_read_only(vma) && pf->access_type != ACCESS_TYPE_READ) { + err = -EPERM; + goto unlock_vm; + } + atomic = access_is_atomic(pf->access_type); if (xe_vma_is_cpu_addr_mirror(vma)) From patchwork Tue Mar 25 22:27:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Cavitt, Jonathan" X-Patchwork-Id: 14029590 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3DF26C36008 for ; Tue, 25 Mar 2025 22:27:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EE41410E610; Tue, 25 Mar 2025 22:27:27 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="amqzq9Pz"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id EE4E210E605; Tue, 25 Mar 2025 22:27:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742941646; x=1774477646; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cgto85fKuTD8MpW293iqRYh8Sld8vy1+NG6nM7iS8z4=; b=amqzq9PzA9y/RBBIRc3q8uTyBw/gbR/cB+sUCoMX0cR99Rb8iMj1qYJT TUbUDmcKGeI5BW2fiO2xLMVFjO7/26MpW/1ENyyTVEXxTOgJzq0kFf0uc MDghMxju3XEOVi6Ibq84G6uAC8tXOfM08LvRZnxqUIFlK+oKdJFDHWwyX 6yNjUH4tgFy51Q+v61U5HSiuwmsXBotZUHf0FNSxthsdCYR91S9XuMj5M RStFm8fvhPoaS1TROZmcGyZMrUwBpPapcoADNNY64Mcus7G4xj1oPUiAr 1sfAK89khYovixGGoDwjsnl1O/uf3UN0rxoJHQPO2YIKflEgG9R9jA8ev A==; X-CSE-ConnectionGUID: +VF4h6mxThKFeFllxxyqNg== X-CSE-MsgGUID: 6GLlOatWTt2kUs5a6Z5wtg== X-IronPort-AV: E=McAfee;i="6700,10204,11384"; a="44369293" X-IronPort-AV: E=Sophos;i="6.14,276,1736841600"; d="scan'208";a="44369293" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2025 15:27:26 -0700 X-CSE-ConnectionGUID: 4ZKpeRDeTQ2PcGoHAnExFw== X-CSE-MsgGUID: K37eJLv0TdGQgRAr8oVd+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,276,1736841600"; d="scan'208";a="129561869" Received: from dut4086lnl.fm.intel.com ([10.105.10.68]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2025 15:27:26 -0700 From: Jonathan Cavitt To: intel-xe@lists.freedesktop.org Cc: saurabhg.gupta@intel.com, alex.zuo@intel.com, jonathan.cavitt@intel.com, joonas.lahtinen@linux.intel.com, matthew.brost@intel.com, jianxun.zhang@intel.com, shuicheng.lin@intel.com, dri-devel@lists.freedesktop.org, Michal.Wajdeczko@intel.com, michal.mrozek@intel.com, raag.jadav@intel.com, john.c.harrison@intel.com Subject: [PATCH v13 3/6] drm/xe/xe_gt_pagefault: Move pagefault struct to header Date: Tue, 25 Mar 2025 22:27:20 +0000 Message-ID: <20250325222724.93226-4-jonathan.cavitt@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250325222724.93226-1-jonathan.cavitt@intel.com> References: <20250325222724.93226-1-jonathan.cavitt@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Move the pagefault struct from xe_gt_pagefault.c to the xe_gt_pagefault_types.h header file, and move the associated enum values into the regs folder under xe_pagefault_desc.h Since xe_pagefault_desc.h is being initialized here, also move the xe_guc_pagefault_desc hardware formats to the new file. v2: - Normalize names for common header (Matt Brost) v3: - s/Migrate/Move (Michal W) - s/xe_pagefault/xe_gt_pagefault (Michal W) - Create new header file, xe_gt_pagefault_types.h (Michal W) - Add kernel docs (Michal W) v4: - Fix includes usage (Michal W) - Reference Bspec (Michal W) v5: - Convert enums to defines in regs folder (Michal W) - Move xe_guc_pagefault_desc to regs folder (Michal W) Bspec: 77412 Signed-off-by: Jonathan Cavitt Cc: Michal Wajdeczko --- drivers/gpu/drm/xe/regs/xe_pagefault_desc.h | 50 +++++++++++++++++++++ drivers/gpu/drm/xe/xe_gt_pagefault.c | 43 ++++-------------- drivers/gpu/drm/xe/xe_gt_pagefault_types.h | 42 +++++++++++++++++ drivers/gpu/drm/xe/xe_guc_fwif.h | 28 ------------ 4 files changed, 101 insertions(+), 62 deletions(-) create mode 100644 drivers/gpu/drm/xe/regs/xe_pagefault_desc.h create mode 100644 drivers/gpu/drm/xe/xe_gt_pagefault_types.h diff --git a/drivers/gpu/drm/xe/regs/xe_pagefault_desc.h b/drivers/gpu/drm/xe/regs/xe_pagefault_desc.h new file mode 100644 index 000000000000..cfa18cb8e8ac --- /dev/null +++ b/drivers/gpu/drm/xe/regs/xe_pagefault_desc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2025 Intel Corporation + */ + +#ifndef _XE_PAGEFAULT_DESC_H_ +#define _XE_PAGEFAULT_DESC_H_ + +#include +#include + +struct xe_guc_pagefault_desc { + u32 dw0; +#define PFD_FAULT_LEVEL GENMASK(2, 0) +#define PFD_SRC_ID GENMASK(10, 3) +#define PFD_RSVD_0 GENMASK(17, 11) +#define XE2_PFD_TRVA_FAULT BIT(18) +#define PFD_ENG_INSTANCE GENMASK(24, 19) +#define PFD_ENG_CLASS GENMASK(27, 25) +#define PFD_PDATA_LO GENMASK(31, 28) + + u32 dw1; +#define PFD_PDATA_HI GENMASK(11, 0) +#define PFD_PDATA_HI_SHIFT 4 +#define PFD_ASID GENMASK(31, 12) + + u32 dw2; +#define PFD_ACCESS_TYPE GENMASK(1, 0) +#define PFD_FAULT_TYPE GENMASK(3, 2) +#define PFD_VFID GENMASK(9, 4) +#define PFD_RSVD_1 BIT(10) +#define XE3P_PFD_PREFETCH BIT(11) +#define PFD_VIRTUAL_ADDR_LO GENMASK(31, 12) +#define PFD_VIRTUAL_ADDR_LO_SHIFT 12 + + u32 dw3; +#define PFD_VIRTUAL_ADDR_HI GENMASK(31, 0) +#define PFD_VIRTUAL_ADDR_HI_SHIFT 32 +} __packed; + +#define FLT_ACCESS_TYPE_READ 0u +#define FLT_ACCESS_TYPE_WRITE 1u +#define FLT_ACCESS_TYPE_ATOMIC 2u +#define FLT_ACCESS_TYPE_RESERVED 3u + +#define FLT_TYPE_NOT_PRESENT_FAULT 0u +#define FLT_TYPE_WRITE_ACCESS_VIOLATION 1u +#define FLT_TYPE_ATOMIC_ACCESS_VIOLATION 2u + +#endif diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c index 3240890aac07..0cedf089a3f2 100644 --- a/drivers/gpu/drm/xe/xe_gt_pagefault.c +++ b/drivers/gpu/drm/xe/xe_gt_pagefault.c @@ -12,8 +12,10 @@ #include #include "abi/guc_actions_abi.h" +#include "regs/xe_pagefault_desc.h" #include "xe_bo.h" #include "xe_gt.h" +#include "xe_gt_pagefault_types.h" #include "xe_gt_stats.h" #include "xe_gt_tlb_invalidation.h" #include "xe_guc.h" @@ -23,33 +25,6 @@ #include "xe_trace_bo.h" #include "xe_vm.h" -struct pagefault { - u64 page_addr; - u32 asid; - u16 pdata; - u8 vfid; - u8 access_type; - u8 fault_type; - u8 fault_level; - u8 engine_class; - u8 engine_instance; - u8 fault_unsuccessful; - bool trva_fault; -}; - -enum access_type { - ACCESS_TYPE_READ = 0, - ACCESS_TYPE_WRITE = 1, - ACCESS_TYPE_ATOMIC = 2, - ACCESS_TYPE_RESERVED = 3, -}; - -enum fault_type { - NOT_PRESENT = 0, - WRITE_ACCESS_VIOLATION = 1, - ATOMIC_ACCESS_VIOLATION = 2, -}; - struct acc { u64 va_range_base; u32 asid; @@ -61,9 +36,9 @@ struct acc { u8 engine_instance; }; -static bool access_is_atomic(enum access_type access_type) +static bool access_is_atomic(u32 access_type) { - return access_type == ACCESS_TYPE_ATOMIC; + return access_type == FLT_ACCESS_TYPE_ATOMIC; } static bool vma_is_valid(struct xe_tile *tile, struct xe_vma *vma) @@ -205,7 +180,7 @@ static struct xe_vm *asid_to_vm(struct xe_device *xe, u32 asid) return vm; } -static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf) +static int handle_pagefault(struct xe_gt *gt, struct xe_gt_pagefault *pf) { struct xe_device *xe = gt_to_xe(gt); struct xe_vm *vm; @@ -237,7 +212,7 @@ static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf) goto unlock_vm; } - if (xe_vma_read_only(vma) && pf->access_type != ACCESS_TYPE_READ) { + if (xe_vma_read_only(vma) && pf->access_type != FLT_ACCESS_TYPE_READ) { err = -EPERM; goto unlock_vm; } @@ -271,7 +246,7 @@ static int send_pagefault_reply(struct xe_guc *guc, return xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0); } -static void print_pagefault(struct xe_device *xe, struct pagefault *pf) +static void print_pagefault(struct xe_device *xe, struct xe_gt_pagefault *pf) { drm_dbg(&xe->drm, "\n\tASID: %d\n" "\tVFID: %d\n" @@ -291,7 +266,7 @@ static void print_pagefault(struct xe_device *xe, struct pagefault *pf) #define PF_MSG_LEN_DW 4 -static bool get_pagefault(struct pf_queue *pf_queue, struct pagefault *pf) +static bool get_pagefault(struct pf_queue *pf_queue, struct xe_gt_pagefault *pf) { const struct xe_guc_pagefault_desc *desc; bool ret = false; @@ -378,7 +353,7 @@ static void pf_queue_work_func(struct work_struct *w) struct xe_gt *gt = pf_queue->gt; struct xe_device *xe = gt_to_xe(gt); struct xe_guc_pagefault_reply reply = {}; - struct pagefault pf = {}; + struct xe_gt_pagefault pf = {}; unsigned long threshold; int ret; diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault_types.h b/drivers/gpu/drm/xe/xe_gt_pagefault_types.h new file mode 100644 index 000000000000..b7d41b558de3 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_gt_pagefault_types.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022-2025 Intel Corporation + */ + +#ifndef _XE_GT_PAGEFAULT_TYPES_H_ +#define _XE_GT_PAGEFAULT_TYPES_H_ + +#include + +/** + * struct xe_gt_pagefault - Structure of pagefaults returned by the + * pagefault handler + */ +struct xe_gt_pagefault { + /** @page_addr: faulted address of this pagefault */ + u64 page_addr; + /** @asid: ASID of this pagefault */ + u32 asid; + /** @pdata: PDATA of this pagefault */ + u16 pdata; + /** @vfid: VFID of this pagefault */ + u8 vfid; + /** @access_type: access type of this pagefault */ + u8 access_type; + /** @fault_type: fault type of this pagefault */ + u8 fault_type; + /** @fault_level: fault level of this pagefault */ + u8 fault_level; + /** @engine_class: engine class this pagefault was reported on */ + u8 engine_class; + /** @engine_instance: engine instance this pagefault was reported on */ + u8 engine_instance; + /** @fault_unsuccessful: flag for if the pagefault recovered or not */ + u8 fault_unsuccessful; + /** @prefetch: unused */ + bool prefetch; + /** @trva_fault: is set if this is a TRTT fault */ + bool trva_fault; +}; + +#endif diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h index 6f57578b07cb..30ac21bb4f15 100644 --- a/drivers/gpu/drm/xe/xe_guc_fwif.h +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h @@ -290,34 +290,6 @@ enum xe_guc_response_desc_type { FAULT_RESPONSE_DESC }; -struct xe_guc_pagefault_desc { - u32 dw0; -#define PFD_FAULT_LEVEL GENMASK(2, 0) -#define PFD_SRC_ID GENMASK(10, 3) -#define PFD_RSVD_0 GENMASK(17, 11) -#define XE2_PFD_TRVA_FAULT BIT(18) -#define PFD_ENG_INSTANCE GENMASK(24, 19) -#define PFD_ENG_CLASS GENMASK(27, 25) -#define PFD_PDATA_LO GENMASK(31, 28) - - u32 dw1; -#define PFD_PDATA_HI GENMASK(11, 0) -#define PFD_PDATA_HI_SHIFT 4 -#define PFD_ASID GENMASK(31, 12) - - u32 dw2; -#define PFD_ACCESS_TYPE GENMASK(1, 0) -#define PFD_FAULT_TYPE GENMASK(3, 2) -#define PFD_VFID GENMASK(9, 4) -#define PFD_RSVD_1 GENMASK(11, 10) -#define PFD_VIRTUAL_ADDR_LO GENMASK(31, 12) -#define PFD_VIRTUAL_ADDR_LO_SHIFT 12 - - u32 dw3; -#define PFD_VIRTUAL_ADDR_HI GENMASK(31, 0) -#define PFD_VIRTUAL_ADDR_HI_SHIFT 32 -} __packed; - struct xe_guc_pagefault_reply { u32 dw0; #define PFR_VALID BIT(0) From patchwork Tue Mar 25 22:27:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Cavitt, Jonathan" X-Patchwork-Id: 14029591 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 65728C36016 for ; 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X-CSE-ConnectionGUID: HmgDBHYvQeua0RCTMzn5hA== X-CSE-MsgGUID: V8OlrUFDQJit3zaXrkC0ow== X-IronPort-AV: E=McAfee;i="6700,10204,11384"; a="44369294" X-IronPort-AV: E=Sophos;i="6.14,276,1736841600"; d="scan'208";a="44369294" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2025 15:27:27 -0700 X-CSE-ConnectionGUID: ou6duot3SE+9+eWZNcIKGw== X-CSE-MsgGUID: 2z9URxx0SAmu1e0I95qfcg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,276,1736841600"; d="scan'208";a="129561873" Received: from dut4086lnl.fm.intel.com ([10.105.10.68]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2025 15:27:26 -0700 From: Jonathan Cavitt To: intel-xe@lists.freedesktop.org Cc: saurabhg.gupta@intel.com, alex.zuo@intel.com, jonathan.cavitt@intel.com, joonas.lahtinen@linux.intel.com, matthew.brost@intel.com, jianxun.zhang@intel.com, shuicheng.lin@intel.com, dri-devel@lists.freedesktop.org, Michal.Wajdeczko@intel.com, michal.mrozek@intel.com, raag.jadav@intel.com, john.c.harrison@intel.com Subject: [PATCH v13 4/6] drm/xe/uapi: Define drm_xe_vm_get_property Date: Tue, 25 Mar 2025 22:27:21 +0000 Message-ID: <20250325222724.93226-5-jonathan.cavitt@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250325222724.93226-1-jonathan.cavitt@intel.com> References: <20250325222724.93226-1-jonathan.cavitt@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add initial declarations for the drm_xe_vm_get_property ioctl. v2: - Expand kernel docs for drm_xe_vm_get_property (Jianxun) v3: - Remove address type external definitions (Jianxun) - Add fault type to xe_drm_fault struct (Jianxun) Signed-off-by: Jonathan Cavitt Cc: Zhang Jianxun --- include/uapi/drm/xe_drm.h | 79 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index 616916985e3f..5817f246e620 100644 --- a/include/uapi/drm/xe_drm.h +++ b/include/uapi/drm/xe_drm.h @@ -81,6 +81,7 @@ extern "C" { * - &DRM_IOCTL_XE_EXEC * - &DRM_IOCTL_XE_WAIT_USER_FENCE * - &DRM_IOCTL_XE_OBSERVATION + * - &DRM_IOCTL_XE_VM_GET_PROPERTY */ /* @@ -102,6 +103,7 @@ extern "C" { #define DRM_XE_EXEC 0x09 #define DRM_XE_WAIT_USER_FENCE 0x0a #define DRM_XE_OBSERVATION 0x0b +#define DRM_XE_VM_GET_PROPERTY 0x0c /* Must be kept compact -- no holes */ @@ -117,6 +119,7 @@ extern "C" { #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) #define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param) +#define DRM_IOCTL_XE_VM_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_GET_PROPERTY, struct drm_xe_vm_get_property) /** * DOC: Xe IOCTL Extensions @@ -1189,6 +1192,82 @@ struct drm_xe_vm_bind { __u64 reserved[2]; }; +/** struct xe_vm_fault - Describes faults for %DRM_XE_VM_GET_PROPERTY_FAULTS */ +struct xe_vm_fault { + /** @address: Address of the fault */ + __u64 address; + /** @address_precision: Precision of faulted address */ + __u32 address_precision; + /** @access_type: Type of address access that resulted in fault */ + __u8 access_type; + /** @fault_type: Type of fault reported */ + __u8 fault_type; + /** @fault_level: fault level of the fault */ + __u8 fault_level; + /** @engine_class: class of engine fault was reported on */ + __u8 engine_class; + /** @engine_instance: instance of engine fault was reported on */ + __u8 engine_instance; + /** @pad: MBZ */ + __u8 pad[7]; + /** @reserved: MBZ */ + __u64 reserved[3]; +}; + +/** + * struct drm_xe_vm_get_property - Input of &DRM_IOCTL_XE_VM_GET_PROPERTY + * + * The user provides a VM and a property to query among DRM_XE_VM_GET_PROPERTY_*, + * and sets the values in the vm_id and property members, respectively. This + * determines both the VM to get the property of, as well as the property to + * report. + * + * If size is set to 0, the driver fills it with the required size for the + * requested property. The user is expected here to allocate memory for the + * property structure and to provide a pointer to the allocated memory using the + * data member. For some properties, this may be zero, in which case, the + * value of the property will be saved to the value member and size will remain + * zero on return. + * + * If size is not zero, then the IOCTL will attempt to copy the requested + * property into the data member. + * + * The IOCTL will return -ENOENT if the VM could not be identified from the + * provided VM ID, or -EINVAL if the IOCTL fails for any other reason, such as + * providing an invalid size for the given property or if the property data + * could not be copied to the memory allocated to the data member. + * + * The property member can be: + * - %DRM_XE_VM_GET_PROPERTY_FAULTS + */ +struct drm_xe_vm_get_property { + /** @extensions: Pointer to the first extension struct, if any */ + __u64 extensions; + + /** @vm_id: The ID of the VM to query the properties of */ + __u32 vm_id; + +#define DRM_XE_VM_GET_PROPERTY_FAULTS 0 + /** @property: property to get */ + __u32 property; + + /** @size: Size to allocate for @data */ + __u32 size; + + /** @pad: MBZ */ + __u32 pad; + + union { + /** @data: Pointer to user-defined array of flexible size and type */ + __u64 data; + /** @value: Return value for scalar queries */ + __u64 value; + }; + + /** @reserved: MBZ */ + __u64 reserved[3]; +}; + /** * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE * From patchwork Tue Mar 25 22:27:22 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Cavitt, Jonathan" X-Patchwork-Id: 14029592 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 649BBC3600E for ; Tue, 25 Mar 2025 22:27:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 818E310E616; Tue, 25 Mar 2025 22:27:28 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="OvyykHZK"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id 87AA410E605; Tue, 25 Mar 2025 22:27:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742941647; x=1774477647; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Mg/VLngH4LbWZiOXGcSujXI8C6fL0j2E//N2ctSgRaM=; b=OvyykHZKSxLa/mJiy1ZyI2ao+D0apBcisWphv34crTMCZEoGwZ0SsP1M +WgXH2GugibezWSSSG/K+s40tutKpfQZBReqAPw7bQWAM3Rpwih2HogKa u2FDMrgN2pq3gQJU/FeWfGtrDoqR70bYjwNKKSwLVIWDgPOTy1Qw6xZbp wnmMH+pbReoBHR7zyOBnNwgIH00Txxcdrb/hsNgSoEAwhb8F08xy+E+o0 eDvLe3RoTjKQRcb2sQl1JGMNn5WkuOnQ44TwiJ19Qow4ggPDlP3u6KWcX qVZqN5Yx4qiJbPJg8zX5hpK2Ls8PHwDgBTlXuji6YPeTGyluRs8pLwUD4 w==; X-CSE-ConnectionGUID: xmTNwMZIRXeKIiUByZ8OSA== X-CSE-MsgGUID: OTL8xPMZQoud67igX69JUQ== X-IronPort-AV: E=McAfee;i="6700,10204,11384"; a="44369295" X-IronPort-AV: E=Sophos;i="6.14,276,1736841600"; d="scan'208";a="44369295" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2025 15:27:27 -0700 X-CSE-ConnectionGUID: 58A04yNFT8aj83AhHAC5LA== X-CSE-MsgGUID: Ee4azxwpT3iou8hSIY16Mg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,276,1736841600"; d="scan'208";a="129561877" Received: from dut4086lnl.fm.intel.com ([10.105.10.68]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2025 15:27:26 -0700 From: Jonathan Cavitt To: intel-xe@lists.freedesktop.org Cc: saurabhg.gupta@intel.com, alex.zuo@intel.com, jonathan.cavitt@intel.com, joonas.lahtinen@linux.intel.com, matthew.brost@intel.com, jianxun.zhang@intel.com, shuicheng.lin@intel.com, dri-devel@lists.freedesktop.org, Michal.Wajdeczko@intel.com, michal.mrozek@intel.com, raag.jadav@intel.com, john.c.harrison@intel.com Subject: [PATCH v13 5/6] drm/xe/xe_vm: Add per VM fault info Date: Tue, 25 Mar 2025 22:27:22 +0000 Message-ID: <20250325222724.93226-6-jonathan.cavitt@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250325222724.93226-1-jonathan.cavitt@intel.com> References: <20250325222724.93226-1-jonathan.cavitt@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add additional information to each VM so they can report up to the first 50 seen faults. Only pagefaults are saved this way currently, though in the future, all faults should be tracked by the VM for future reporting. Additionally, of the pagefaults reported, only failed pagefaults are saved this way, as successful pagefaults should recover silently and not need to be reported to userspace. v2: - Free vm after use (Shuicheng) - Compress pf copy logic (Shuicheng) - Update fault_unsuccessful before storing (Shuicheng) - Fix old struct name in comments (Shuicheng) - Keep first 50 pagefaults instead of last 50 (Jianxun) v3: - Avoid unnecessary execution by checking MAX_PFS earlier (jcavitt) - Fix double-locking error (jcavitt) - Assert kmemdump is successful (Shuicheng) v4: - Rename xe_vm.pfs to xe_vm.faults (jcavitt) - Store fault data and not pagefault in xe_vm faults list (jcavitt) - Store address, address type, and address precision per fault (jcavitt) - Store engine class and instance data per fault (Jianxun) - Add and fix kernel docs (Michal W) - Properly handle kzalloc error (Michal W) - s/MAX_PFS/MAX_FAULTS_SAVED_PER_VM (Michal W) - Store fault level per fault (Micahl M) v5: - Store fault and access type instead of address type (Jianxun) v6: - Store pagefaults in non-fault-mode VMs as well (Jianxun) v7: - Fix kernel docs and comments (Michal W) Signed-off-by: Jonathan Cavitt Suggested-by: Matthew Brost Cc: Shuicheng Lin Cc: Jianxun Zhang Cc: Michal Wajdeczko Cc: Michal Mzorek --- drivers/gpu/drm/xe/xe_gt_pagefault.c | 34 ++++++++++++++++ drivers/gpu/drm/xe/xe_vm.c | 60 ++++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_vm.h | 9 +++++ drivers/gpu/drm/xe/xe_vm_types.h | 32 +++++++++++++++ 4 files changed, 135 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_gt_pagefault.c b/drivers/gpu/drm/xe/xe_gt_pagefault.c index 0cedf089a3f2..102d6e2b6def 100644 --- a/drivers/gpu/drm/xe/xe_gt_pagefault.c +++ b/drivers/gpu/drm/xe/xe_gt_pagefault.c @@ -345,6 +345,39 @@ int xe_guc_pagefault_handler(struct xe_guc *guc, u32 *msg, u32 len) return full ? -ENOSPC : 0; } +static void save_pagefault_to_vm(struct xe_device *xe, struct xe_gt_pagefault *pf) +{ + struct xe_vm *vm; + + /* + * Pagefault may be associated to VM that is not in fault mode. + * Perform asid_to_vm behavior, except if vm is not in fault + * mode, return the VM anyways. + */ + down_read(&xe->usm.lock); + vm = xa_load(&xe->usm.asid_to_vm, pf->asid); + if (vm) + xe_vm_get(vm); + else + vm = ERR_PTR(-EINVAL); + up_read(&xe->usm.lock); + + if (IS_ERR(vm)) + return; + + spin_lock(&vm->faults.lock); + + /* + * Limit the number of faults in the fault list to prevent + * memory overuse. + */ + if (vm->faults.len < MAX_FAULTS_SAVED_PER_VM) + xe_vm_add_fault_entry_pf(vm, pf); + + spin_unlock(&vm->faults.lock); + xe_vm_put(vm); +} + #define USM_QUEUE_MAX_RUNTIME_MS 20 static void pf_queue_work_func(struct work_struct *w) @@ -364,6 +397,7 @@ static void pf_queue_work_func(struct work_struct *w) if (unlikely(ret)) { print_pagefault(xe, &pf); pf.fault_unsuccessful = 1; + save_pagefault_to_vm(xe, &pf); drm_dbg(&xe->drm, "Fault response: Unsuccessful %d\n", ret); } diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c index 793f5bc393c2..2c89af125a90 100644 --- a/drivers/gpu/drm/xe/xe_vm.c +++ b/drivers/gpu/drm/xe/xe_vm.c @@ -28,6 +28,7 @@ #include "xe_drm_client.h" #include "xe_exec_queue.h" #include "xe_gt_pagefault.h" +#include "xe_gt_pagefault_types.h" #include "xe_gt_tlb_invalidation.h" #include "xe_migrate.h" #include "xe_pat.h" @@ -778,6 +779,60 @@ int xe_vm_userptr_check_repin(struct xe_vm *vm) list_empty_careful(&vm->userptr.invalidated)) ? 0 : -EAGAIN; } +/** + * xe_vm_add_fault_entry_pf() - Add pagefault to vm fault list + * @vm: The VM. + * @pf: The pagefault. + * + * This function takes the data from the pagefault @pf and saves it to @vm->faults.list. + * + * The function exits silently if the list is full, and reports a warning if the pagefault + * could not be saved to the list. + */ +void xe_vm_add_fault_entry_pf(struct xe_vm *vm, struct xe_gt_pagefault *pf) +{ + struct xe_vm_fault_entry *e = NULL; + + spin_lock(&vm->faults.lock); + + if (vm->faults.len >= MAX_FAULTS_SAVED_PER_VM) + goto out; + + e = kzalloc(sizeof(*e), GFP_KERNEL); + if (!e) { + drm_warn(&vm->xe->drm, + "Could not allocate memory for fault %i!", + vm->faults.len); + goto out; + } + + e->address = pf->page_addr; + e->address_precision = 1; + e->access_type = pf->access_type; + e->fault_type = pf->fault_type; + e->fault_level = pf->fault_level; + e->engine_class = pf->engine_class; + e->engine_instance = pf->engine_instance; + + list_add_tail(&e->list, &vm->faults.list); + vm->faults.len++; +out: + spin_unlock(&vm->faults.lock); +} + +static void xe_vm_clear_fault_entries(struct xe_vm *vm) +{ + struct xe_vm_fault_entry *e, *tmp; + + spin_lock(&vm->faults.lock); + list_for_each_entry_safe(e, tmp, &vm->faults.list, list) { + list_del(&e->list); + kfree(e); + } + vm->faults.len = 0; + spin_unlock(&vm->faults.lock); +} + static int xe_vma_ops_alloc(struct xe_vma_ops *vops, bool array_of_binds) { int i; @@ -1660,6 +1715,9 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags) init_rwsem(&vm->userptr.notifier_lock); spin_lock_init(&vm->userptr.invalidated_lock); + INIT_LIST_HEAD(&vm->faults.list); + spin_lock_init(&vm->faults.lock); + ttm_lru_bulk_move_init(&vm->lru_bulk_move); INIT_WORK(&vm->destroy_work, vm_destroy_work_func); @@ -1930,6 +1988,8 @@ void xe_vm_close_and_put(struct xe_vm *vm) } up_write(&xe->usm.lock); + xe_vm_clear_fault_entries(vm); + for_each_tile(tile, xe, id) xe_range_fence_tree_fini(&vm->rftree[id]); diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h index 0ef811fc2bde..9bd7e93824da 100644 --- a/drivers/gpu/drm/xe/xe_vm.h +++ b/drivers/gpu/drm/xe/xe_vm.h @@ -12,6 +12,12 @@ #include "xe_map.h" #include "xe_vm_types.h" +/** + * MAX_FAULTS_SAVED_PER_VM - Maximum number of faults each vm can store before future + * faults are discarded to prevent memory overuse + */ +#define MAX_FAULTS_SAVED_PER_VM 50 + struct drm_device; struct drm_printer; struct drm_file; @@ -22,6 +28,7 @@ struct dma_fence; struct xe_exec_queue; struct xe_file; +struct xe_gt_pagefault; struct xe_sync_entry; struct xe_svm_range; struct drm_exec; @@ -257,6 +264,8 @@ int xe_vma_userptr_pin_pages(struct xe_userptr_vma *uvma); int xe_vma_userptr_check_repin(struct xe_userptr_vma *uvma); +void xe_vm_add_fault_entry_pf(struct xe_vm *vm, struct xe_gt_pagefault *pf); + bool xe_vm_validate_should_retry(struct drm_exec *exec, int err, ktime_t *end); int xe_vm_lock_vma(struct drm_exec *exec, struct xe_vma *vma); diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h index 84fa41b9fa20..5e9bb0052f69 100644 --- a/drivers/gpu/drm/xe/xe_vm_types.h +++ b/drivers/gpu/drm/xe/xe_vm_types.h @@ -19,6 +19,7 @@ #include "xe_range_fence.h" struct xe_bo; +struct xe_pagefault; struct xe_svm_range; struct xe_sync_entry; struct xe_user_fence; @@ -142,6 +143,27 @@ struct xe_userptr_vma { struct xe_device; +/** + * struct xe_vm_fault_entry - Elements of vm->faults.list + * @list: link into @xe_vm.faults.list + * @address: address of the fault + * @address_type: type of address access that resulted in fault + * @address_precision: precision of faulted address + * @fault_level: fault level of the fault + * @engine_class: class of engine fault was reported on + * @engine_instance: instance of engine fault was reported on + */ +struct xe_vm_fault_entry { + struct list_head list; + u64 address; + u32 address_precision; + u8 access_type; + u8 fault_type; + u8 fault_level; + u8 engine_class; + u8 engine_instance; +}; + struct xe_vm { /** @gpuvm: base GPUVM used to track VMAs */ struct drm_gpuvm gpuvm; @@ -305,6 +327,16 @@ struct xe_vm { bool capture_once; } error_capture; + /** @faults: List of all faults associated with this VM */ + struct { + /** @faults.lock: lock protecting @faults.list */ + spinlock_t lock; + /** @faults.list: list of xe_vm_fault_entry entries */ + struct list_head list; + /** @faults.len: length of @faults.list */ + unsigned int len; + } faults; + /** * @tlb_flush_seqno: Required TLB flush seqno for the next exec. * protected by the vm resv. From patchwork Tue Mar 25 22:27:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Cavitt, Jonathan" X-Patchwork-Id: 14029593 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3505FC36005 for ; Tue, 25 Mar 2025 22:27:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 03ED910E619; Tue, 25 Mar 2025 22:27:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="c1wZy0m1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by gabe.freedesktop.org (Postfix) with ESMTPS id DBB7C10E605; Tue, 25 Mar 2025 22:27:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742941647; x=1774477647; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gaFvPlOI+RVLA2TrJE4oWhCsNvEzXaJz/EBAT1367Yc=; b=c1wZy0m1SFSAq4XOe3xfXZABi49/5wkOGuHTiIle+P1Y/f4ElWa7Jcsl BOijCi7F8oF/9fBKOXkSr1xkK1f0BnyrUnpFF7QN4Ctym7DAmiCsqt92G GlQYzUg4qi674Et2aWZf0aEPnzW3QBCTVeaVz+2tuPWCkQilVK6VpkXYf +bfDNeLaPGEo/qULbqpL6gBic1eH8PIEpCaa9Coxp4Y6M+wdoo73bmpo9 AiJ8/OpM5JKL+fgfQS8AdGfwPkxYjp5Lu/KfdpZc/lqT3gHHbefwmltOI LrHL8vybVJQ01d9iVNRrrxBVN5TgDi3L5Zrv2LloKFteuh951dEXoBeEq w==; X-CSE-ConnectionGUID: cdv+tFuiSkW9YacIEfbqdw== X-CSE-MsgGUID: wc7MmYdoSxmNoPQVQl+RKQ== X-IronPort-AV: E=McAfee;i="6700,10204,11384"; a="44369296" X-IronPort-AV: E=Sophos;i="6.14,276,1736841600"; d="scan'208";a="44369296" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2025 15:27:27 -0700 X-CSE-ConnectionGUID: 1jJd4BK9Q0u1Xu8he2pB0Q== X-CSE-MsgGUID: UJQxNtzLTxO4/nRQ9anuTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,276,1736841600"; d="scan'208";a="129561880" Received: from dut4086lnl.fm.intel.com ([10.105.10.68]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2025 15:27:27 -0700 From: Jonathan Cavitt To: intel-xe@lists.freedesktop.org Cc: saurabhg.gupta@intel.com, alex.zuo@intel.com, jonathan.cavitt@intel.com, joonas.lahtinen@linux.intel.com, matthew.brost@intel.com, jianxun.zhang@intel.com, shuicheng.lin@intel.com, dri-devel@lists.freedesktop.org, Michal.Wajdeczko@intel.com, michal.mrozek@intel.com, raag.jadav@intel.com, john.c.harrison@intel.com Subject: [PATCH v13 6/6] drm/xe/xe_vm: Implement xe_vm_get_property_ioctl Date: Tue, 25 Mar 2025 22:27:23 +0000 Message-ID: <20250325222724.93226-7-jonathan.cavitt@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250325222724.93226-1-jonathan.cavitt@intel.com> References: <20250325222724.93226-1-jonathan.cavitt@intel.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add support for userspace to request a list of observed faults from a specified VM. v2: - Only allow querying of failed pagefaults (Matt Brost) v3: - Remove unnecessary size parameter from helper function, as it is a property of the arguments. (jcavitt) - Remove unnecessary copy_from_user (Jainxun) - Set address_precision to 1 (Jainxun) - Report max size instead of dynamic size for memory allocation purposes. Total memory usage is reported separately. v4: - Return int from xe_vm_get_property_size (Shuicheng) - Fix memory leak (Shuicheng) - Remove unnecessary size variable (jcavitt) v5: - Rename ioctl to xe_vm_get_faults_ioctl (jcavitt) - Update fill_property_pfs to eliminate need for kzalloc (Jianxun) v6: - Repair and move fill_faults break condition (Dan Carpenter) - Free vm after use (jcavitt) - Combine assertions (jcavitt) - Expand size check in xe_vm_get_faults_ioctl (jcavitt) - Remove return mask from fill_faults, as return is already -EFAULT or 0 (jcavitt) v7: - Revert back to using xe_vm_get_property_ioctl - Apply better copy_to_user logic (jcavitt) v8: - Fix and clean up error value handling in ioctl (jcavitt) - Reapply return mask for fill_faults (jcavitt) v9: - Future-proof size logic for zero-size properties (jcavitt) - Add access and fault types (Jianxun) - Remove address type (Jianxun) v10: - Remove unnecessary switch case logic (Raag) - Compress size get, size validation, and property fill functions into a single helper function (jcavitt) - Assert valid size (jcavitt) v11: - Remove unnecessary else condition - Correct backwards helper function size logic (jcavitt) Signed-off-by: Jonathan Cavitt Suggested-by: Matthew Brost Cc: Jainxun Zhang Cc: Shuicheng Lin Cc: Raag Jadav --- drivers/gpu/drm/xe/xe_device.c | 3 ++ drivers/gpu/drm/xe/xe_vm.c | 88 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_vm.h | 2 + 3 files changed, 93 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 1ffb7d1f6be6..02f84a855502 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -195,6 +195,9 @@ static const struct drm_ioctl_desc xe_ioctls[] = { DRM_IOCTL_DEF_DRV(XE_WAIT_USER_FENCE, xe_wait_user_fence_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(XE_OBSERVATION, xe_observation_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(XE_VM_GET_PROPERTY, xe_vm_get_property_ioctl, + DRM_RENDER_ALLOW), + }; static long xe_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c index 2c89af125a90..d57aa24a5de8 100644 --- a/drivers/gpu/drm/xe/xe_vm.c +++ b/drivers/gpu/drm/xe/xe_vm.c @@ -3553,6 +3553,94 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) return err; } +static int fill_faults(struct xe_vm *vm, + struct drm_xe_vm_get_property *args) +{ + struct xe_vm_fault __user *usr_ptr = u64_to_user_ptr(args->data); + struct xe_vm_fault store = { 0 }; + struct xe_vm_fault_entry *entry; + int ret = 0, i = 0, count, entry_size; + + entry_size = sizeof(struct xe_vm_fault); + count = args->size / entry_size; + + spin_lock(&vm->faults.lock); + list_for_each_entry(entry, &vm->faults.list, list) { + if (i++ == count) + break; + + memset(&store, 0, entry_size); + + store.address = entry->address; + store.address_precision = entry->address_precision; + store.access_type = entry->access_type; + store.fault_type = entry->fault_type; + store.fault_level = entry->fault_level; + store.engine_class = xe_to_user_engine_class[entry->engine_class]; + store.engine_instance = entry->engine_instance; + + ret = copy_to_user(usr_ptr, &store, entry_size); + if (ret) + break; + + usr_ptr++; + } + spin_unlock(&vm->faults.lock); + + return ret ? -EFAULT : 0; +} + +static int xe_vm_get_property_helper(struct xe_vm *vm, + struct drm_xe_vm_get_property *args) +{ + int size; + + switch (args->property) { + case DRM_XE_VM_GET_PROPERTY_FAULTS: + spin_lock(&vm->faults.lock); + size = size_mul(sizeof(struct xe_vm_fault), vm->faults.len); + spin_unlock(&vm->faults.lock); + + if (args->size) + /* + * Number of faults may increase between calls to + * xe_vm_get_property_ioctl, so just report the + * number of faults the user requests if it's less + * than or equal to the number of faults in the VM + * fault array. + */ + return args->size <= size ? fill_faults(vm, args) : -EINVAL; + + args->size = size; + return 0; + } + return -EINVAL; +} + +int xe_vm_get_property_ioctl(struct drm_device *drm, void *data, + struct drm_file *file) +{ + struct xe_device *xe = to_xe_device(drm); + struct xe_file *xef = to_xe_file(file); + struct drm_xe_vm_get_property *args = data; + struct xe_vm *vm; + int ret = 0; + + if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) + return -EINVAL; + if (XE_IOCTL_DBG(xe, args->size < 0)) + return -EINVAL; + + vm = xe_vm_lookup(xef, args->vm_id); + if (XE_IOCTL_DBG(xe, !vm)) + return -ENOENT; + + ret = xe_vm_get_property_helper(vm, args); + + xe_vm_put(vm); + return ret; +} + /** * xe_vm_bind_kernel_bo - bind a kernel BO to a VM * @vm: VM to bind the BO to diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h index 9bd7e93824da..63ec22458e04 100644 --- a/drivers/gpu/drm/xe/xe_vm.h +++ b/drivers/gpu/drm/xe/xe_vm.h @@ -196,6 +196,8 @@ int xe_vm_destroy_ioctl(struct drm_device *dev, void *data, struct drm_file *file); int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file); +int xe_vm_get_property_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); void xe_vm_close_and_put(struct xe_vm *vm);