From patchwork Wed Mar 26 23:40:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 14030601 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 66CF3C36008 for ; Wed, 26 Mar 2025 23:40:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 033EA10E14A; Wed, 26 Mar 2025 23:40:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="e+pS+w+Z"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3808A10E78F; Wed, 26 Mar 2025 23:40:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743032425; x=1774568425; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rYtTDqGZk/TIzquJnB/YyFAgaI5FpwJfM3wQVdO94DM=; b=e+pS+w+ZITXSVac6nmQuHmTMZLpDR6cT4DHP1WoxjcgJYZJ66Z52M4Ui fii/3y3lwGQSsPY7Yges7qAgmtcYpINQYx2RS3uAWCOoEbTTlvd2mk6V9 NaVXPRr5EiIaopbUC8c7pZCCQN4fr/iEApsy81gyDUt/5c+V8bglb7Lef 1nne/OR/AwDeR/tTxydfoCi34vkIvzwswQ+Y3hIQfiNrNGWmooj/2u7+s EGruy71VfikCytUE78Zf56U8pl3olE1ogaIZDchfEpCUE3fPHFf0g48rT zxfdaDMnEeoJQgJCsTMitCSR7YKtSEScJ4S4FvpItJ1FLt3bqnc+wn13H Q==; X-CSE-ConnectionGUID: cFR5AlO+QciY8MCS1ZCYqQ== X-CSE-MsgGUID: YPlw8Z8BTwCDjeq/4Rc4+Q== X-IronPort-AV: E=McAfee;i="6700,10204,11385"; a="61741383" X-IronPort-AV: E=Sophos;i="6.14,279,1736841600"; d="scan'208";a="61741383" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 16:40:24 -0700 X-CSE-ConnectionGUID: 7z0pEnsMRBiNUcgo8sCebw== X-CSE-MsgGUID: gX2rGes2S76uyOOacXslYg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,279,1736841600"; d="scan'208";a="148143243" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.3]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 16:40:21 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Arshad Mehmood , Chris Wilson , Lucas De Marchi , Andi Shyti , Andi Shyti Subject: [PATCH v2 1/6] drm/i915: Add the FIRST_CCS() helper Date: Thu, 27 Mar 2025 00:40:00 +0100 Message-ID: <20250326234005.1574688-2-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250326234005.1574688-1-andi.shyti@linux.intel.com> References: <20250326234005.1574688-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Andi Shyti Some GPUs, like DG2, can host more than one CCS engine. Some workarounds or enablements need to happen only once for all the engines in the GT—for example, on the engine with the lowest instance. The FIRST_CCS() helper first checks if the engine is a Compute engine, and then whether it's the one with the lowest instance. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 54538b6f85df..5cb501393c4b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -619,6 +619,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define CCS_MASK(gt) \ ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) +#define FIRST_CCS(e__) \ + (CCS_MASK(e__->gt) && (__ffs(CCS_MASK(e__->gt)) == e__->instance)) + #define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode) /* From patchwork Wed Mar 26 23:40:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 14030602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75BF9C3600B for ; Wed, 26 Mar 2025 23:40:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 10BA710E0B5; Wed, 26 Mar 2025 23:40:31 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Tlj4FsAW"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 00A5110E790; Wed, 26 Mar 2025 23:40:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743032430; x=1774568430; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wsY7/a57B+Q4orM/dKPI0qWfy0Ki0gfoCnRBLRVtxVM=; b=Tlj4FsAWUYP1eG5UG/3qhnzP5DbaHJN9Vf7R+25vMuCJgbDOuqy4K7iK 0WfzwZsMsqqXfSdGY3Dqapqb7uVhklrbxNLSnmOFIAMSH8/ZH53tzH06B NQVKrq66OIGG2QIU9q1aArxiTY1rSwO+GFgUl4qyYtWEbtcpn4Xt+laN7 u7H7MxMi/lB3D+r2nYGho8ei3f/10oeTbvbulhtQtsUmajh4Joy5dwsgw OSEmeGQFAeohgLLy3b5DDAsg2KJKdv6gFdQVn7xkbZ+9cIO1iJY6/4/ZU WNKBgEJ/Zzs4uhdTL62+YfB6qTW2iy4jGQM1VLbVB51rDDEg+7dtppfWW w==; X-CSE-ConnectionGUID: JBRp/LO8QNaPMPdNG32XzQ== X-CSE-MsgGUID: VvRiBhI7Q1Kf73zedErZBQ== X-IronPort-AV: E=McAfee;i="6700,10204,11385"; a="61741389" X-IronPort-AV: E=Sophos;i="6.14,279,1736841600"; d="scan'208";a="61741389" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 16:40:30 -0700 X-CSE-ConnectionGUID: ysikK+AfR7yIts5VjGojZA== X-CSE-MsgGUID: WrsXmiutQDWtQIG949dI1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,279,1736841600"; d="scan'208";a="148143275" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.3]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 16:40:27 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Arshad Mehmood , Chris Wilson , Lucas De Marchi , Andi Shyti , Andi Shyti Subject: [PATCH v2 2/6] drm/i915/gt: Move CCS workaround to the correct section Date: Thu, 27 Mar 2025 00:40:01 +0100 Message-ID: <20250326234005.1574688-3-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250326234005.1574688-1-andi.shyti@linux.intel.com> References: <20250326234005.1574688-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The CCS engine workaround was previously added in a section shared by both RCS and CCS engines. Move it to the proper CCS-specific section so that it's applied only once, avoiding unintended duplication caused by the first CCS/RCS detection check. To do this, the ccs_mode() function had to be moved earlier in the file to avoid the need for a forward declaration. Suggested-by: Arshad Mehmood Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 58 +++++++++++---------- 1 file changed, 30 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 116683ebe074..bedd88a15959 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2699,10 +2699,38 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) XEHP_BLITTER_ROUND_ROBIN_MODE); } +static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) +{ + struct intel_gt *gt = engine->gt; + u32 mode; + + /* + * This workaround should be applied only once across all + * CCS engines. Apply it to the first CCS encountered. + */ + if (!FIRST_CCS(engine)) + return; + + /* + * Wa_14019159160: This workaround, along with others, leads to + * significant challenges in utilizing load balancing among the + * CCS slices. Consequently, an architectural decision has been + * made to completely disable automatic CCS load balancing. + */ + wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE); + + /* + * After having disabled automatic load balancing we need to + * assign all slices to a single CCS. We will call it CCS mode 1 + */ + mode = intel_gt_apply_ccs_mode(gt); + wa_masked_en(wal, XEHP_CCS_MODE, mode); +} + static void ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) { - /* boilerplate for any CCS engine workaround */ + ccs_engine_wa_mode(engine, wal); } /* @@ -2739,30 +2767,6 @@ add_render_compute_tuning_settings(struct intel_gt *gt, wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC); } -static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) -{ - struct intel_gt *gt = engine->gt; - u32 mode; - - if (!IS_DG2(gt->i915)) - return; - - /* - * Wa_14019159160: This workaround, along with others, leads to - * significant challenges in utilizing load balancing among the - * CCS slices. Consequently, an architectural decision has been - * made to completely disable automatic CCS load balancing. - */ - wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE); - - /* - * After having disabled automatic load balancing we need to - * assign all slices to a single CCS. We will call it CCS mode 1 - */ - mode = intel_gt_apply_ccs_mode(gt); - wa_masked_en(wal, XEHP_CCS_MODE, mode); -} - /* * The workarounds in this function apply to shared registers in * the general render reset domain that aren't tied to a @@ -2895,10 +2899,8 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal * to a single RCS/CCS engine's workaround list since * they're reset as part of the general render domain reset. */ - if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) { + if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) general_render_compute_wa_init(engine, wal); - ccs_engine_wa_mode(engine, wal); - } if (engine->class == COMPUTE_CLASS) ccs_engine_wa_init(engine, wal); From patchwork Wed Mar 26 23:40:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 14030603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3CC09C36008 for ; Wed, 26 Mar 2025 23:40:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C7CA610E78F; Wed, 26 Mar 2025 23:40:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="g8TC6PUJ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F9A010E78E; Wed, 26 Mar 2025 23:40:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743032436; x=1774568436; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2AIHpEEKnnHKbHbHSpBkIqoXJrvfxlWzMZC0AU2+S7I=; b=g8TC6PUJp1WVK32nrLbBjwHv0erMMq/SthkIkCp+ThxGlXjmPP83jTPo 0csrcWsHXECNRBKpEgEkwjhgUYIZ7aajX2iutMq/Jk3GEi8kmGdWkaFrw LwqSIjjOkVKxpby1tpAntB13gesv87hRubrKhvhanufrLJgBwAVc80M33 bbIY2KcZuIXKzV+k9ZSD+I3P1SgLA9FuduLlCTkiEnHzQaJXC05Y17TnO IycVrX/MjG+kjcAGc726JZOk1AKOTrRLSITYAXzoi2dBN4TaxhE+a/1Vr a3gNRmGSAtTL2m86lFuhkiXTtFFngclTJypQS4blSrweld6GZMfhQFR7a Q==; X-CSE-ConnectionGUID: 1ZdxOO3dTbuwuceWZab/dA== X-CSE-MsgGUID: 201Bvn06TOikaqJ1TFuJzg== X-IronPort-AV: E=McAfee;i="6700,10204,11385"; a="61741396" X-IronPort-AV: E=Sophos;i="6.14,279,1736841600"; d="scan'208";a="61741396" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 16:40:36 -0700 X-CSE-ConnectionGUID: PXQ5QOKcT/yu7/YIZzmAuQ== X-CSE-MsgGUID: /AUaDAo7S8uuORo/8wWo5g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,279,1736841600"; d="scan'208";a="148143298" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.3]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 16:40:33 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Arshad Mehmood , Chris Wilson , Lucas De Marchi , Andi Shyti , Andi Shyti Subject: [PATCH v2 3/6] drm/i915/gt: Remove FIRST_RENDER_COMPUTE in workaround Date: Thu, 27 Mar 2025 00:40:02 +0100 Message-ID: <20250326234005.1574688-4-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250326234005.1574688-1-andi.shyti@linux.intel.com> References: <20250326234005.1574688-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Andi Shyti All platforms supported by i915 have at least one RCS engine, so there's no need to explicitly check for RCS or CCS presence. Remove the redundant check and move the associated functions to a more appropriate location in the code. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index bedd88a15959..b8ea6505afa2 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2894,20 +2894,14 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal engine_fake_wa_init(engine, wal); - /* - * These are common workarounds that just need to applied - * to a single RCS/CCS engine's workaround list since - * they're reset as part of the general render domain reset. - */ - if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) + if (engine->class == RENDER_CLASS) { general_render_compute_wa_init(engine, wal); - - if (engine->class == COMPUTE_CLASS) - ccs_engine_wa_init(engine, wal); - else if (engine->class == RENDER_CLASS) rcs_engine_wa_init(engine, wal); - else + } else if (engine->class == COMPUTE_CLASS) { + ccs_engine_wa_init(engine, wal); + } else { xcs_engine_wa_init(engine, wal); + } } void intel_engine_init_workarounds(struct intel_engine_cs *engine) From patchwork Wed Mar 26 23:40:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 14030604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26079C36008 for ; Wed, 26 Mar 2025 23:40:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B047210E11A; Wed, 26 Mar 2025 23:40:42 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="h19SNizu"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7728410E796; Wed, 26 Mar 2025 23:40:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743032442; x=1774568442; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KGfy8w8eDrctc2a+UsExK692S5f4DDJVOJ8XaYF8b7c=; b=h19SNizua6v3QDN1al471ApokRCJ3qqBeUU2XoAvMrmQimwVNkqRKBLF la8M2j2190iFrHUzRY3y2eYJ1LNrR+0XkM9Ubm8OST1bHNagFrfEkgyim ytGCJBt7PexhNRozfhQrKEv1lzga+cC6XEss6pSp0h76j3jZRjWDkNs6h TAe1nw7k49DX59+nG9+x821qBqFIGL3Gb5YUTzbI3FVUBmDpfLqn053C+ A6/Gn6sBeOQ9CHnRmoRjp1SAq3/dxhnjeIKnL/N//un0JMK99x8FAWIEG u1857EUgZdeODanq1MjRUEQ8Z5TMDJe6c7gm1tzgar9opSnc8vddqJnrV g==; X-CSE-ConnectionGUID: GxbVZiLfS6SXVID+mFkb1g== X-CSE-MsgGUID: rxF4YVKWTb6MYPJtm/ib+g== X-IronPort-AV: E=McAfee;i="6700,10204,11385"; a="61741409" X-IronPort-AV: E=Sophos;i="6.14,279,1736841600"; d="scan'208";a="61741409" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 16:40:41 -0700 X-CSE-ConnectionGUID: JJw/AOMBRsqYs4+x/ZL1fg== X-CSE-MsgGUID: vlXvVP/4RBKCf1i65SMlFw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,279,1736841600"; d="scan'208";a="148143319" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.3]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 16:40:39 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Arshad Mehmood , Chris Wilson , Lucas De Marchi , Andi Shyti , Andi Shyti Subject: [PATCH v2 4/6] drm/i915/gt: Check for the first CCS instead of FIRST_RENDER_COMPUTE Date: Thu, 27 Mar 2025 00:40:03 +0100 Message-ID: <20250326234005.1574688-5-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250326234005.1574688-1-andi.shyti@linux.intel.com> References: <20250326234005.1574688-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Andi Shyti Enable the CCS engine when the first CCS is encountered in the execlist setup, instead of checking for the I915_ENGINE_FIRST_RENDER_COMPUTE flag. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 4a80ffa1b962..70ea56054a19 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2950,7 +2950,7 @@ static int execlists_resume(struct intel_engine_cs *engine) enable_execlists(engine); - if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) + if (FIRST_CCS(engine)) xehp_enable_ccs_engines(engine); return 0; From patchwork Wed Mar 26 23:40:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 14030605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5AE1BC36008 for ; Wed, 26 Mar 2025 23:40:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EE9E410E795; Wed, 26 Mar 2025 23:40:48 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Pd6WgXwf"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id CA00610E796; Wed, 26 Mar 2025 23:40:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743032448; x=1774568448; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pP5/UWSGcS8q2Imu26bLoyXiWQfUfxs2LGdRR/o8DGM=; b=Pd6WgXwfmQyeg+vV1KjqIj+nysw5g+/pSGzjvEHQvjfRTuMFX7m3ZA4N +oY02dNqi8YHFHEwvj0fi8NTIVhmLu1UURUbcDT9SGhooF3WqhZp8sahn /0Km1MuD69UCgoAyM6UuHeJb86EO9IicpqkukZ/W8jGDZk7NJnhYzoURr 2H60PoO5xWb5gRh9R0ammEsxeEBwPKmtCQGi0yX4g8orPCGtHGu9C59Fq OB7sN536bP82n7TMny774VKa+9jY9uhB+uYdEbDIp2v9sA7nI6K7FmEfK a07t7N4ohDQQqsiXnXjjXtDmIi+risM/Ci0E5yb+thB2KDfvirCjn1GZo w==; X-CSE-ConnectionGUID: 3ebyTjXHR3uV+nD2KMLlMA== X-CSE-MsgGUID: f0MjF32SS6+IlQ7plD1atw== X-IronPort-AV: E=McAfee;i="6700,10204,11385"; a="61741445" X-IronPort-AV: E=Sophos;i="6.14,279,1736841600"; d="scan'208";a="61741445" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 16:40:48 -0700 X-CSE-ConnectionGUID: gwO0MftlTjWa1rJHfpPGOg== X-CSE-MsgGUID: NRtEeMzURNaQf9MaUaAScw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,279,1736841600"; d="scan'208";a="148143333" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.3]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 16:40:45 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Arshad Mehmood , Chris Wilson , Lucas De Marchi , Andi Shyti , Andi Shyti Subject: [PATCH v2 5/6] drm/i915/gt/uc: Use FIRST_CCS() helper for one-time CCS operations Date: Thu, 27 Mar 2025 00:40:04 +0100 Message-ID: <20250326234005.1574688-6-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250326234005.1574688-1-andi.shyti@linux.intel.com> References: <20250326234005.1574688-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Andi Shyti Replace checks for I915_ENGINE_FIRST_RENDER_COMPUTE combined with CCS_MASK() with the FIRST_CCS() helper. This improves readability and ensures that certain CCS-specific actions, such as enabling GEN12_RCU_MODE and calling xehp_enable_ccs_engines(), are performed only once, on the first CCS engine encountered. This is particularly relevant for platforms like DG2, which support multiple CCS engines. Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +-- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 46fabbfc775e..bf1686af29e7 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -392,8 +392,7 @@ static int guc_mmio_regset_init(struct temp_regset *regset, ret |= GUC_MMIO_REG_ADD(gt, regset, RING_HWS_PGA(base), false); ret |= GUC_MMIO_REG_ADD(gt, regset, RING_IMR(base), false); - if ((engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) && - CCS_MASK(engine->gt)) + if (FIRST_CCS(engine)) ret |= GUC_MMIO_REG_ADD(gt, regset, GEN12_RCU_MODE, true); /* diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index f8cb7c630d5b..18545196c9f4 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -4422,7 +4422,7 @@ static int guc_resume(struct intel_engine_cs *engine) setup_hwsp(engine); start_engine(engine); - if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) + if (FIRST_CCS(engine)) xehp_enable_ccs_engines(engine); return 0; From patchwork Wed Mar 26 23:40:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 14030606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82816C3600E for ; Wed, 26 Mar 2025 23:40:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1B67D10E79C; Wed, 26 Mar 2025 23:40:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="k8GVMRIV"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F8D610E797; Wed, 26 Mar 2025 23:40:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743032453; x=1774568453; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=V2hIantJs/ba1zTI8XaNyTzBKndiBQRmCbgC6UJbNUE=; b=k8GVMRIV72fEyIg3jLglNUJ/e2ycCzJydPFTrWDK5MQBvjc8nqpJQ3Yg gpwdCpNTzaQCct+kijvlC92/f13ojNBrw5Oo/wJRFoM3HwnPWQQl4K5JP J5ZaZvShfsMdqD0db2aNKOv9RkPuYdfGMK/RJs/UBbJCD0QYXHr8Ert5D a6mdh0wL5Uw7PN+cNds2y4F1vuZbizLNB85xwJDe3vnJrHd+Vdm9nPhkH OQQ4lhxicHls9VPDl0chzyeWkJjJv0TG8yx2vfCmnLOUqagTnTrk9bTx6 qRa2gNr043LIPphSputWCC3n+Ld5+/1pG/PZqf0+EtJ6VJ7vb1NohNAd5 A==; X-CSE-ConnectionGUID: +mbLaiT4Q7SnrN0g97ssVQ== X-CSE-MsgGUID: hqLOTkZ0RMCfwvy/CznEZA== X-IronPort-AV: E=McAfee;i="6700,10204,11385"; a="44236851" X-IronPort-AV: E=Sophos;i="6.14,279,1736841600"; d="scan'208";a="44236851" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 16:40:53 -0700 X-CSE-ConnectionGUID: Z5NwH3EtToeJAUjTLLkGuQ== X-CSE-MsgGUID: wUj3M/t8Q/iCjqnS78Bk0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,279,1736841600"; d="scan'208";a="125146910" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.3]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2025 16:40:50 -0700 From: Andi Shyti To: intel-gfx , dri-devel Cc: Arshad Mehmood , Chris Wilson , Lucas De Marchi , Andi Shyti , Andi Shyti Subject: [PATCH v2 6/6] drm/i915/gt: Remove unused I915_ENGINE_FIRST_RENDER_COMPUTE flag Date: Thu, 27 Mar 2025 00:40:05 +0100 Message-ID: <20250326234005.1574688-7-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250326234005.1574688-1-andi.shyti@linux.intel.com> References: <20250326234005.1574688-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Andi Shyti The I915_ENGINE_FIRST_RENDER_COMPUTE flag is no longer used. Its purpose has been replaced by the FIRST_CCS() helper, which determines the first render or compute engine as needed. Remove the flag definition and its assignment from intel_engine_setup(). Suggested-by: Lucas De Marchi Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ---- drivers/gpu/drm/i915/gt/intel_engine_types.h | 3 +-- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index b721bbd23356..1b60be057192 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -497,10 +497,6 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, engine->logical_mask = BIT(logical_instance); __sprint_engine_name(engine); - if ((engine->class == COMPUTE_CLASS || engine->class == RENDER_CLASS) && - __ffs(CCS_MASK(engine->gt) | RCS_MASK(engine->gt)) == engine->instance) - engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE; - /* features common between engines sharing EUs */ if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) { engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE; diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index 155b6255a63e..c5529b966b7a 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -590,8 +590,7 @@ struct intel_engine_cs { #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8) #define I915_ENGINE_HAS_RCS_REG_STATE BIT(9) #define I915_ENGINE_HAS_EU_PRIORITY BIT(10) -#define I915_ENGINE_FIRST_RENDER_COMPUTE BIT(11) -#define I915_ENGINE_USES_WA_HOLD_SWITCHOUT BIT(12) +#define I915_ENGINE_USES_WA_HOLD_SWITCHOUT BIT(11) unsigned int flags; /*