From patchwork Thu Mar 27 14:46:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14031224 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1ADD6C36013 for ; Thu, 27 Mar 2025 14:58:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AE6E910E8F8; Thu, 27 Mar 2025 14:58:20 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="TxaVVzgw"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0770D10E068; Thu, 27 Mar 2025 14:58:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743087498; x=1774623498; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hpV5fEyd87hT0Mbf8iHgJhG7WJR0dZycnDG0D8+RChs=; b=TxaVVzgwI6jYNmz1/6eM69ZSr1O8YYQelwrysUKcjTVl4h8Ydt5jYsVz iiABItzUIjCRclwGSlRl7gYxv+XfqL2vg2v9pK8g0Nvj7qESLLhvzr9+m a9N1Kj2vW0JdsqW6GjJTPockm3FE89uWI4iI90cmAJsdqm9PXGRqtdA1t Z+tkmxXC0Firn6iVszd5NIZGGCHOb9xchL2xzgw9DTnExGU48Dnf1zkY5 Of//6x0i4tOnq90tZdkPqM2YVOKLs11ZBpsMqxZKcABmHG7AiJUoA9ZSH wnppmaoP+1gU8MH0Ge5FAhsK35wZHxHfkscANZUN2v/6P0Vx8OakeDpbc g==; X-CSE-ConnectionGUID: FIikk085Rw+4wcaLAutLwg== X-CSE-MsgGUID: 2sL4Ums/QDWmtnSpJIKAEg== X-IronPort-AV: E=McAfee;i="6700,10204,11385"; a="69788016" X-IronPort-AV: E=Sophos;i="6.14,280,1736841600"; d="scan'208";a="69788016" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Mar 2025 07:58:18 -0700 X-CSE-ConnectionGUID: 60Jcb+qsQ6i1nkqpr6cGcw== X-CSE-MsgGUID: TLW6P3HXS2KtswAzWbd2zA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,280,1736841600"; d="scan'208";a="125381250" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Mar 2025 07:58:16 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 1/2] drm/i915/display: Introduce transcoder_has_vrr() helper Date: Thu, 27 Mar 2025 20:16:28 +0530 Message-ID: <20250327144629.648306-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250327144629.648306-1-ankit.k.nautiyal@intel.com> References: <20250327144629.648306-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Introduce a new helper to check transcoder_has_vrr() and use that to exclude transcoders which do not support VRR. v2: Include HAS_VRR into the helper. (Ville) v3: Drop the usage in places where not applicable. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ee7812126129..b82b3d63be73 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2625,6 +2625,15 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, PIPE_LINK_N2(display, transcoder)); } +static bool +transcoder_has_vrr(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + return HAS_VRR(display) && !transcoder_is_dsi(cpu_transcoder); +} + static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -3908,7 +3917,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, DISPLAY_VER(display) >= 11) intel_get_transcoder_timings(crtc, pipe_config); - if (HAS_VRR(display) && !transcoder_is_dsi(pipe_config->cpu_transcoder)) + if (transcoder_has_vrr(pipe_config)) intel_vrr_get_config(pipe_config); intel_get_pipe_src_size(crtc, pipe_config); From patchwork Thu Mar 27 14:46:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 14031225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3EE79C36011 for ; Thu, 27 Mar 2025 14:58:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CE81C10E8FC; Thu, 27 Mar 2025 14:58:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="czOobY6A"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2FAF010E8F8; Thu, 27 Mar 2025 14:58:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743087500; x=1774623500; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=maXhYlV18eQ6CmLzEeOQvWLX73fzDb9hIlKZ9FOoaCA=; b=czOobY6AplNIR8sIwDtd38WBTVylB/HaJ81Giu+CGkEIcVbpk8Tj3iMh PKMkz9K1OvF++rDtGAx1in8c1tYVXJK2PldqQsimoMjrFRA/9jroWXT3y LUBh9wqiCSDvfXAyd0Vx1OLBznQ2UOpBTBHogxgBIvy3ZDJBkYqIcLLh0 SXOgXtB7M6Tjx+8kDapqSC8wv/a36Qd5Nl0tOV/7l59NF6lTILdV0tGlr 72EGqhQ7u2R24UDa6za6mZPAIgFPALCtIAmaLzccYzW3fbsdJM9ulAZQ8 uhLfOgNeADX/CuJZstFjPMaHl7gp+pe6JQE6n2hrYz91WVq1RKhSsnP51 g==; X-CSE-ConnectionGUID: QaayyOPwQUquxfeOJOdMIA== X-CSE-MsgGUID: bOwpC+4RQ3GFWoZ4aRwHxA== X-IronPort-AV: E=McAfee;i="6700,10204,11385"; a="69788022" X-IronPort-AV: E=Sophos;i="6.14,280,1736841600"; d="scan'208";a="69788022" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Mar 2025 07:58:20 -0700 X-CSE-ConnectionGUID: KNH60ncKSbi4/uCaWRhnww== X-CSE-MsgGUID: DkNJvb1aT/Sk9A9pr6MErg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,280,1736841600"; d="scan'208";a="125381260" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Mar 2025 07:58:18 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, ville.syrjala@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: [PATCH 2/2] drm/i915/display: Avoid use of VTOTAL.Vtotal bits Date: Thu, 27 Mar 2025 20:16:29 +0530 Message-ID: <20250327144629.648306-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250327144629.648306-1-ankit.k.nautiyal@intel.com> References: <20250327144629.648306-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal bits are not required. Since the support for these bits is going to be deprecated in upcoming platforms, avoid writing these bits for the platforms that do not use legacy Timing Generator. Since for these platforms vrr.vmin is always filled with crtc_vtotal, use TRAN_VRR_VMIN to get the vtotal for adjusted_mode. v2: Avoid having a helper for manipulating VTOTAL register, and instead just make the change where required. (Ville) v3: Set crtc_vtotal instead of working with the bits directly (Ville). Use intel_vrr_vmin_vtotal() to set the vtotal during readout. (Ville) v4: Keep the reading part unchanged, and let it get overwritten for cases where we use vrr.vmin. (Ville) Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++++++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b82b3d63be73..b447fca1c616 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2698,6 +2698,15 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); + /* + * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal + * bits are not required. Since the support for these bits is going to + * be deprecated in upcoming platforms, avoid writing these bits for the + * platforms that do not use legacy Timing Generator. + */ + if (intel_vrr_always_use_vrr_tg(display)) + crtc_vtotal = 1; + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); @@ -2758,6 +2767,15 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), VBLANK_START(crtc_vblank_start - 1) | VBLANK_END(crtc_vblank_end - 1)); + /* + * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal + * bits are not required. Since the support for these bits is going to + * be deprecated in upcoming platforms, avoid writing these bits for the + * platforms that do not use legacy Timing Generator. + */ + if (intel_vrr_always_use_vrr_tg(display)) + crtc_vtotal = 1; + /* * The double buffer latch point for TRANS_VTOTAL * is the transcoder's undelayed vblank. diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 414f93851059..7359d66fc091 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -708,6 +708,16 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.vmin = intel_de_read(display, TRANS_VRR_VMIN(display, cpu_transcoder)) + 1; + /* + * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal + * bits are not filled. Since for these platforms TRAN_VMIN is always + * filled with crtc_vtotal, use TRAN_VRR_VMIN to get the vtotal for + * adjusted_mode. + */ + if (intel_vrr_always_use_vrr_tg(display)) + crtc_state->hw.adjusted_mode.crtc_vtotal = + intel_vrr_vmin_vtotal(crtc_state); + if (HAS_AS_SDP(display)) { trans_vrr_vsync = intel_de_read(display,