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Parse timebase-frequency properpy of /cpus node to initialize cpu_khz variable. 2. Initialize boot_clock_cycles with the current time counter value to have starting point for Xen. timebase-frequency is read as a uint32_t because it is unlikely that the timer will run at more than 4 GHz. If timebase-frequency exceeds 4 GHz, a panic() is triggered, since dt_property_read_u32() will return 0 if the size of the timebase-frequency property is greater than the size of the output variable. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v3: - s/xen_start_clock_cycles/boot_clock_cycles - Add panic() in preinit_xen_time() for the case when acpi_disabled = false. - Change type of boot_clokc_cycles to uint64_t as the counter will be still 64-bit for RV32. Add inclusion of xen/types.h for uint64_t. - Move definition of timer variable to preinit_dt_xen_time() as there is no any reason to be a file scope variable. - Update the commit message. --- Changes in v2: - Update SPDX tag for time.c - s/read_mostly/__ro_after_init for boot_count variable. - Add declaration of boot_count to asm/time.h. - Rename boot_count to xen_start_clock_cycles. - Stray double blank in the defintion of timer_ids. - s/u32/uint32_t. - Drop full stop. - Update the commit message. - s/__initconst/__initconstrel for timer_ids[]. --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/include/asm/time.h | 6 +++++ xen/arch/riscv/setup.c | 2 ++ xen/arch/riscv/stubs.c | 2 -- xen/arch/riscv/time.c | 42 +++++++++++++++++++++++++++++++ 5 files changed, 51 insertions(+), 2 deletions(-) create mode 100644 xen/arch/riscv/time.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index b0c8270a99..82016a957a 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -9,6 +9,7 @@ obj-y += setup.o obj-y += shutdown.o obj-y += smp.o obj-y += stubs.o +obj-y += time.o obj-y += traps.o obj-y += vm_event.o diff --git a/xen/arch/riscv/include/asm/time.h b/xen/arch/riscv/include/asm/time.h index fc1572e9b4..e8d9ffec57 100644 --- a/xen/arch/riscv/include/asm/time.h +++ b/xen/arch/riscv/include/asm/time.h @@ -3,8 +3,12 @@ #define ASM__RISCV__TIME_H #include +#include #include +/* Clock cycles count at Xen startup */ +extern uint64_t boot_clock_cycles; + struct vcpu; static inline void force_update_vcpu_system_time(struct vcpu *v) @@ -19,6 +23,8 @@ static inline cycles_t get_cycles(void) return csr_read(CSR_TIME); } +void preinit_xen_time(void); + #endif /* ASM__RISCV__TIME_H */ /* diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index b0e587678e..836ad16fed 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -126,6 +126,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, riscv_fill_hwcap(); + preinit_xen_time(); + printk("All set up\n"); machine_halt(); diff --git a/xen/arch/riscv/stubs.c b/xen/arch/riscv/stubs.c index 5951b0ce91..caa133de84 100644 --- a/xen/arch/riscv/stubs.c +++ b/xen/arch/riscv/stubs.c @@ -27,8 +27,6 @@ nodemask_t __read_mostly node_online_map = { { [0] = 1UL } }; /* time.c */ -unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ - s_time_t get_s_time(void) { BUG_ON("unimplemented"); diff --git a/xen/arch/riscv/time.c b/xen/arch/riscv/time.c new file mode 100644 index 0000000000..905bb13eb4 --- /dev/null +++ b/xen/arch/riscv/time.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include +#include +#include + +unsigned long __ro_after_init cpu_khz; /* CPU clock frequency in kHz. */ +uint64_t __ro_after_init boot_clock_cycles; + +/* Set up the timer on the boot CPU (early init function) */ +static void __init preinit_dt_xen_time(void) +{ + static const struct dt_device_match __initconstrel timer_ids[] = + { + DT_MATCH_PATH("/cpus"), + { /* sentinel */ }, + }; + struct dt_device_node *timer; + uint32_t rate; + + timer = dt_find_matching_node(NULL, timer_ids); + if ( !timer ) + panic("Unable to find a compatible timer in the device tree\n"); + + dt_device_set_used_by(timer, DOMID_XEN); + + if ( !dt_property_read_u32(timer, "timebase-frequency", &rate) ) + panic("Unable to find clock frequency\n"); + + cpu_khz = rate / 1000; +} + +void __init preinit_xen_time(void) +{ + if ( acpi_disabled ) + preinit_dt_xen_time(); + else + panic("%s: ACPI isn't supported\n", __func__); + + boot_clock_cycles = get_cycles(); +} From patchwork Fri Mar 28 16:58:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14032250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A962BC36011 for ; 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However, since PLIC is now considered obsolete and will not be supported by Xen now, APLIC and IMSIC are selected instead to manage both wired interrupts and MSIs. Signed-off-by: Oleksii Kurochko Acked-by: Andrew Cooper --- Tests results: https://gitlab.com/xen-project/people/olkur/xen/-/pipelines/1734636979 Based on the source code of Qemu the support of AIA should be present from 7.0.0: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") ``` $ git tag --contains 28d8c281200f20a060c456c81fd1564f3d119fda staging-mjt-test trivial-patches-pull-request v7.0.0 v7.0.0-rc0 v7.0.0-rc1 v7.0.0-rc2 v7.0.0-rc3 v7.0.0-rc4 v7.1.0 ... ``` And in Xen's GitLab CI it is used 7.2.11: ``` $ CONTAINER_NO_PULL=1 CONTAINER=bookworm-riscv64 ./automation/scripts/containerize *** Launching container ... user@6a1d1f0077fe:/build$ qemu-system-riscv64 --version QEMU emulator version 7.2.11 (Debian 1:7.2+dfsg-7+deb12u6) Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers ``` --- Changes in v3: - Nothing changed. Only rebase. --- Changes in v2: - Acked-by: Andrew Cooper --- automation/scripts/qemu-smoke-riscv64.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/automation/scripts/qemu-smoke-riscv64.sh b/automation/scripts/qemu-smoke-riscv64.sh index 8f755d0a6a..b2e112c942 100755 --- a/automation/scripts/qemu-smoke-riscv64.sh +++ b/automation/scripts/qemu-smoke-riscv64.sh @@ -6,7 +6,7 @@ set -ex -o pipefail rm -f smoke.serial export TEST_CMD="qemu-system-riscv64 \ - -M virt \ + -M virt,aia=aplic-imsic \ -smp 1 \ -nographic \ -m 2g \ From patchwork Fri Mar 28 16:58:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14032253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7F9CC36016 for ; Fri, 28 Mar 2025 16:58:54 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.930972.1333476 (Exim 4.92) (envelope-from ) id 1tyD2X-0001BN-Dv; Fri, 28 Mar 2025 16:58:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 930972.1333476; Fri, 28 Mar 2025 16:58:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tyD2X-00019h-8C; Fri, 28 Mar 2025 16:58:41 +0000 Received: by outflank-mailman (input) for mailman id 930972; Fri, 28 Mar 2025 16:58:40 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tyD2W-00011d-Ch for xen-devel@lists.xenproject.org; Fri, 28 Mar 2025 16:58:40 +0000 Received: from mail-ed1-x535.google.com (mail-ed1-x535.google.com [2a00:1450:4864:20::535]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e5b09478-0bf5-11f0-9ea4-5ba50f476ded; Fri, 28 Mar 2025 17:58:39 +0100 (CET) Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-5edc07c777eso1645393a12.3 for ; Fri, 28 Mar 2025 09:58:39 -0700 (PDT) Received: from fedora.. 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Since Microchip originally developed aplic.c [1], an internal discussion with them led to the decision to use the MIT license instead of the default GPL-2.0-only. [1] https://gitlab.com/xen-project/people/olkur/xen/-/commit/7cfb4bd4748ca268142497ac5c327d2766fb342d Co-developed-by: Romain Caritey Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v3: - Add _ro_after_init for aplic_info variable. - Add inclusion of xen/sections.h. - Change S-off-by to Co-developed-by after the discusstion wirh Romain C. - Add Acked-by: Jan Beulich . --- Changes in v2: - drop initialization of .node member to NULL of aplic_info. - s/initcont/initconstrel for aplic_dt_match and put initconstrel between type and identifier. - Update identation for DT_DEVICE_START(aplic, ...). - Update the commit message. --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/aplic.c | 50 +++++++++++++++++++++++++++++++ xen/arch/riscv/include/asm/intc.h | 20 +++++++++++++ 3 files changed, 71 insertions(+) create mode 100644 xen/arch/riscv/aplic.c create mode 100644 xen/arch/riscv/include/asm/intc.h diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index 82016a957a..dd5fd25c7d 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -1,3 +1,4 @@ +obj-y += aplic.o obj-y += cpufeature.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += entry.o diff --git a/xen/arch/riscv/aplic.c b/xen/arch/riscv/aplic.c new file mode 100644 index 0000000000..caba8f8993 --- /dev/null +++ b/xen/arch/riscv/aplic.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: MIT */ + +/* + * xen/arch/riscv/aplic.c + * + * RISC-V Advanced Platform-Level Interrupt Controller support + * + * Copyright (c) 2023-2024 Microchip. + * Copyright (c) 2024-2025 Vates + */ + +#include +#include +#include +#include + +#include +#include + +static struct intc_info __ro_after_init aplic_info = { + .hw_version = INTC_APLIC, +}; + +static int __init aplic_preinit(struct dt_device_node *node, const void *dat) +{ + if ( aplic_info.node ) + { + printk("XEN doesn't support more than one S mode APLIC\n"); + return -ENODEV; + } + + /* don't process if APLIC node is not for S mode */ + if ( dt_get_property(node, "riscv,children", NULL) ) + return -ENODEV; + + aplic_info.node = node; + + return 0; +} + +static const struct dt_device_match __initconstrel aplic_dt_match[] = +{ + DT_MATCH_COMPATIBLE("riscv,aplic"), + { /* sentinel */ }, +}; + +DT_DEVICE_START(aplic, "APLIC", DEVICE_INTERRUPT_CONTROLLER) + .dt_match = aplic_dt_match, + .init = aplic_preinit, +DT_DEVICE_END diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm/intc.h new file mode 100644 index 0000000000..ff9bb33896 --- /dev/null +++ b/xen/arch/riscv/include/asm/intc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: MIT */ + +/* + * (c) 2023-2024 Microchip Technology Inc. + * (c) 2024 Vates + */ + +#ifndef ASM__RISCV__INTERRUPT_CONTOLLER_H +#define ASM__RISCV__INTERRUPT_CONTOLLER_H + +enum intc_version { + INTC_APLIC, +}; + +struct intc_info { + enum intc_version hw_version; + const struct dt_device_node *node; +}; + +#endif /* ASM__RISCV__INTERRUPT_CONTOLLER_H */ From patchwork Fri Mar 28 16:58:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleksii Kurochko X-Patchwork-Id: 14032251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 993F4C36013 for ; Fri, 28 Mar 2025 16:58:54 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.930973.1333493 (Exim 4.92) (envelope-from ) id 1tyD2Y-0001hs-Kw; Fri, 28 Mar 2025 16:58:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 930973.1333493; Fri, 28 Mar 2025 16:58:42 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tyD2Y-0001hh-Hw; Fri, 28 Mar 2025 16:58:42 +0000 Received: by outflank-mailman (input) for mailman id 930973; Fri, 28 Mar 2025 16:58:41 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1tyD2X-00011d-GG for xen-devel@lists.xenproject.org; Fri, 28 Mar 2025 16:58:41 +0000 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [2a00:1450:4864:20::52b]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id e65dbb7e-0bf5-11f0-9ea4-5ba50f476ded; Fri, 28 Mar 2025 17:58:41 +0100 (CET) Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-5eb5ecf3217so4399092a12.3 for ; Fri, 28 Mar 2025 09:58:40 -0700 (PDT) Received: from fedora.. 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When `acpi_disabled` is true, the system will scan for a node with the "interrupt-controller" property and then call `device_init()` to validate if it is an expected interrupt controller and if yes then save this node for further usage. If `acpi_disabled` is false, the system will panic, as ACPI support is not yet implemented for RISC-V. Signed-off-by: Oleksii Kurochko Acked-by: Jan Beulich --- Changes in v3: - Add Acked-by: Jan Beulich . --- Changes in v2: - Update the commit message. --- xen/arch/riscv/Makefile | 1 + xen/arch/riscv/include/asm/intc.h | 2 ++ xen/arch/riscv/intc.c | 14 ++++++++++++++ xen/arch/riscv/setup.c | 3 +++ 4 files changed, 20 insertions(+) create mode 100644 xen/arch/riscv/intc.c diff --git a/xen/arch/riscv/Makefile b/xen/arch/riscv/Makefile index dd5fd25c7d..0c6c4a38a3 100644 --- a/xen/arch/riscv/Makefile +++ b/xen/arch/riscv/Makefile @@ -2,6 +2,7 @@ obj-y += aplic.o obj-y += cpufeature.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += entry.o +obj-y += intc.o obj-y += mm.o obj-y += pt.o obj-$(CONFIG_RISCV_64) += riscv64/ diff --git a/xen/arch/riscv/include/asm/intc.h b/xen/arch/riscv/include/asm/intc.h index ff9bb33896..52ba196d87 100644 --- a/xen/arch/riscv/include/asm/intc.h +++ b/xen/arch/riscv/include/asm/intc.h @@ -17,4 +17,6 @@ struct intc_info { const struct dt_device_node *node; }; +void intc_preinit(void); + #endif /* ASM__RISCV__INTERRUPT_CONTOLLER_H */ diff --git a/xen/arch/riscv/intc.c b/xen/arch/riscv/intc.c new file mode 100644 index 0000000000..4061a3c457 --- /dev/null +++ b/xen/arch/riscv/intc.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void __init intc_preinit(void) +{ + if ( acpi_disabled ) + intc_dt_preinit(); + else + panic("ACPI interrupt controller preinit() isn't implemented\n"); +} diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c index 836ad16fed..4e416f6e44 100644 --- a/xen/arch/riscv/setup.c +++ b/xen/arch/riscv/setup.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -128,6 +129,8 @@ void __init noreturn start_xen(unsigned long bootcpu_id, preinit_xen_time(); + intc_preinit(); + printk("All set up\n"); machine_halt();