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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3d5d5a74286sm6769405ab.39.2025.03.28.14.02.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 14:02:38 -0700 (PDT) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/7] dt-bindings: soc: spacemit: define spacemit,k1-ccu resets Date: Fri, 28 Mar 2025 16:02:26 -0500 Message-ID: <20250328210233.1077035-2-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250328210233.1077035-1-elder@riscstar.com> References: <20250328210233.1077035-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There are additional SpacemiT syscon CCUs whose registers control both clocks and resets: RCPU, RCPU2, and APBC2. Unlike those defined previously, these will initially support only resets. They do not incorporate power domain functionality. Define the index values for resets associated with all SpacemiT K1 syscon nodes, including those with clocks already defined, as well as the new ones (without clocks). Signed-off-by: Alex Elder Reviewed-by: Rob Herring (Arm) --- v2: - Names are now RESET_* rather than RST_* - Added Rob's Reviewed-by tag .../soc/spacemit/spacemit,k1-syscon.yaml | 13 +- include/dt-bindings/clock/spacemit,k1-ccu.h | 128 ++++++++++++++++++ 2 files changed, 137 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml index 07a6728e6f864..333c28e075b6c 100644 --- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml @@ -19,6 +19,9 @@ properties: - spacemit,k1-syscon-apbc - spacemit,k1-syscon-apmu - spacemit,k1-syscon-mpmu + - spacemit,k1-syscon-rcpu + - spacemit,k1-syscon-rcpu2 + - spacemit,k1-syscon-apbc2 reg: maxItems: 1 @@ -57,13 +60,15 @@ allOf: properties: compatible: contains: - const: spacemit,k1-syscon-apbc + enum: + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu then: - properties: - "#power-domain-cells": false - else: required: - "#power-domain-cells" + else: + properties: + "#power-domain-cells": false additionalProperties: false diff --git a/include/dt-bindings/clock/spacemit,k1-ccu.h b/include/dt-bindings/clock/spacemit,k1-ccu.h index 4a0c7163257e3..a4f68cba44d1b 100644 --- a/include/dt-bindings/clock/spacemit,k1-ccu.h +++ b/include/dt-bindings/clock/spacemit,k1-ccu.h @@ -78,6 +78,9 @@ #define CLK_APB 31 #define CLK_WDT_BUS 32 +/* MPMU resets */ +#define RESET_WDT 0 + /* APBC clocks */ #define CLK_UART0 0 #define CLK_UART2 1 @@ -180,6 +183,59 @@ #define CLK_TSEN_BUS 98 #define CLK_IPC_AP2AUD_BUS 99 +/* APBC resets */ +#define RESET_UART0 0 +#define RESET_UART2 1 +#define RESET_UART3 2 +#define RESET_UART4 3 +#define RESET_UART5 4 +#define RESET_UART6 5 +#define RESET_UART7 6 +#define RESET_UART8 7 +#define RESET_UART9 8 +#define RESET_GPIO 9 +#define RESET_PWM0 10 +#define RESET_PWM1 11 +#define RESET_PWM2 12 +#define RESET_PWM3 13 +#define RESET_PWM4 14 +#define RESET_PWM5 15 +#define RESET_PWM6 16 +#define RESET_PWM7 17 +#define RESET_PWM8 18 +#define RESET_PWM9 19 +#define RESET_PWM10 20 +#define RESET_PWM11 21 +#define RESET_PWM12 22 +#define RESET_PWM13 23 +#define RESET_PWM14 24 +#define RESET_PWM15 25 +#define RESET_PWM16 26 +#define RESET_PWM17 27 +#define RESET_PWM18 28 +#define RESET_PWM19 29 +#define RESET_SSP3 30 +#define RESET_RTC 31 +#define RESET_TWSI0 32 +#define RESET_TWSI1 33 +#define RESET_TWSI2 34 +#define RESET_TWSI4 35 +#define RESET_TWSI5 36 +#define RESET_TWSI6 37 +#define RESET_TWSI7 38 +#define RESET_TWSI8 39 +#define RESET_TIMERS1 40 +#define RESET_TIMERS2 41 +#define RESET_AIB 42 +#define RESET_ONEWIRE 43 +#define RESET_SSPA0 44 +#define RESET_SSPA1 45 +#define RESET_DRO 46 +#define RESET_IR 47 +#define RESET_TSEN 48 +#define RESET_IPC_AP2AUD 49 +#define RESET_CAN0 50 + /* APMU clocks */ #define CLK_CCI550 0 #define CLK_CPU_C0_HI 1 @@ -244,4 +300,76 @@ #define CLK_V2D 60 #define CLK_EMMC_BUS 61 +/* APMU resets */ +#define RESET_CCIC_4X 0 +#define RESET_CCIC1_PHY 1 +#define RESET_SDH_AXI 2 +#define RESET_SDH0 3 +#define RESET_SDH1 4 +#define RESET_SDH2 5 +#define RESET_USBP1_AXI 6 +#define RESET_USB_AXI 7 +#define RESET_USB3_0 8 +#define RESET_QSPI 9 +#define RESET_QSPI_BUS 10 +#define RESET_DMA 11 +#define RESET_AES 12 +#define RESET_VPU 13 +#define RESET_GPU 14 +#define RESET_EMMC 15 +#define RESET_EMMC_X 16 +#define RESET_AUDIO 17 +#define RESET_HDMI 18 +#define RESET_PCIE0 19 +#define RESET_PCIE1 20 +#define RESET_PCIE2 21 +#define RESET_EMAC0 22 +#define RESET_EMAC1 23 +#define RESET_JPG 24 +#define RESET_CCIC2PHY 25 +#define RESET_CCIC3PHY 26 +#define RESET_CSI 27 +#define RESET_ISP_CPP 28 +#define RESET_ISP_BUS 29 +#define RESET_ISP 30 +#define RESET_ISP_CI 31 +#define RESET_DPU_MCLK 32 +#define RESET_DPU_ESC 33 +#define RESET_DPU_HCLK 34 +#define RESET_DPU_SPIBUS 35 +#define RESET_DPU_SPI_HBUS 36 +#define RESET_V2D 37 +#define RESET_MIPI 38 +#define RESET_MC 39 + +/* RCPU resets */ +#define RESET_RCPU_SSP0 0 +#define RESET_RCPU_I2C0 1 +#define RESET_RCPU_UART1 2 +#define RESET_RCPU_IR 3 +#define RESET_RCPU_CAN 4 +#define RESET_RCPU_UART0 5 +#define RESET_RCPU_HDMI_AUDIO 6 + +/* RCPU2 resets */ +#define RESET_RCPU2_PWM0 0 +#define RESET_RCPU2_PWM1 1 +#define RESET_RCPU2_PWM2 2 +#define RESET_RCPU2_PWM3 3 +#define RESET_RCPU2_PWM4 4 +#define RESET_RCPU2_PWM5 5 +#define RESET_RCPU2_PWM6 6 +#define RESET_RCPU2_PWM7 7 +#define RESET_RCPU2_PWM8 8 +#define RESET_RCPU2_PWM9 9 + +/* APBC2 resets */ +#define RESET_APBC2_UART1 0 +#define RESET_APBC2_SSP2 1 +#define RESET_APBC2_TWSI3 2 +#define RESET_APBC2_RTC 3 +#define RESET_APBC2_TIMERS0 4 +#define RESET_APBC2_KPC 5 +#define RESET_APBC2_GPIO 6 + #endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */ From patchwork Fri Mar 28 21:02:27 2025 Content-Type: text/plain; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3d5d5a74286sm6769405ab.39.2025.03.28.14.02.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 14:02:39 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/7] clk: spacemit: define struct spacemit_ccu_data Date: Fri, 28 Mar 2025 16:02:27 -0500 Message-ID: <20250328210233.1077035-3-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250328210233.1077035-1-elder@riscstar.com> References: <20250328210233.1077035-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Define a new structure type to be used for describing the OF match data. Rather than using the array of spacemit_ccu_clk structures for match data, we use this structure instead. Move the definition of the spacemit_ccu_clk structure closer to the top of the source file, and add the new structure definition below it. Signed-off-by: Alex Elder --- v2: - New structure is called spacemit_ccu_data, not k1_ccu_data - Don't check for a null match data pointer; add a comment instead drivers/clk/spacemit/ccu-k1.c | 55 ++++++++++++++++++++++++++--------- 1 file changed, 41 insertions(+), 14 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 44db48ae71313..5cadb395a7dd6 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -129,6 +129,15 @@ #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec +struct spacemit_ccu_clk { + int id; + struct clk_hw *hw; +}; + +struct spacemit_ccu_data { + struct spacemit_ccu_clk *clk; /* array with sentinel */ +}; + /* APBS clocks start */ /* Frequency of pll{1,2} should not be updated at runtime */ @@ -1359,11 +1368,6 @@ static CCU_GATE_DEFINE(emmc_bus_clk, CCU_PARENT_HW(pmua_aclk), 0); /* APMU clocks end */ -struct spacemit_ccu_clk { - int id; - struct clk_hw *hw; -}; - static struct spacemit_ccu_clk k1_ccu_apbs_clks[] = { { CLK_PLL1, &pll1.common.hw }, { CLK_PLL2, &pll2.common.hw }, @@ -1403,6 +1407,10 @@ static struct spacemit_ccu_clk k1_ccu_apbs_clks[] = { { 0, NULL }, }; +static const struct spacemit_ccu_data k1_ccu_apbs_data = { + .clk = k1_ccu_apbs_clks, +}; + static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] = { { CLK_PLL1_307P2, &pll1_d8_307p2.common.hw }, { CLK_PLL1_76P8, &pll1_d32_76p8.common.hw }, @@ -1440,6 +1448,10 @@ static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] = { { 0, NULL }, }; +static const struct spacemit_ccu_data k1_ccu_mpmu_data = { + .clk = k1_ccu_mpmu_clks, +}; + static struct spacemit_ccu_clk k1_ccu_apbc_clks[] = { { CLK_UART0, &uart0_clk.common.hw }, { CLK_UART2, &uart2_clk.common.hw }, @@ -1544,6 +1556,10 @@ static struct spacemit_ccu_clk k1_ccu_apbc_clks[] = { { 0, NULL }, }; +static const struct spacemit_ccu_data k1_ccu_apbc_data = { + .clk = k1_ccu_apbc_clks, +}; + static struct spacemit_ccu_clk k1_ccu_apmu_clks[] = { { CLK_CCI550, &cci550_clk.common.hw }, { CLK_CPU_C0_HI, &cpu_c0_hi_clk.common.hw }, @@ -1610,9 +1626,13 @@ static struct spacemit_ccu_clk k1_ccu_apmu_clks[] = { { 0, NULL }, }; +static const struct spacemit_ccu_data k1_ccu_apmu_data = { + .clk = k1_ccu_apmu_clks, +}; + static int spacemit_ccu_register(struct device *dev, struct regmap *regmap, struct regmap *lock_regmap, - const struct spacemit_ccu_clk *clks) + struct spacemit_ccu_clk *clks) { const struct spacemit_ccu_clk *clk; int i, ret, max_id = 0; @@ -1648,15 +1668,22 @@ static int spacemit_ccu_register(struct device *dev, clk_data->num = max_id + 1; - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret) + dev_err(dev, "error %d adding clock hardware provider\n", ret); + + return ret; } static int k1_ccu_probe(struct platform_device *pdev) { struct regmap *base_regmap, *lock_regmap = NULL; + const struct spacemit_ccu_data *data; struct device *dev = &pdev->dev; int ret; + data = of_device_get_match_data(dev); + base_regmap = device_node_to_regmap(dev->of_node); if (IS_ERR(base_regmap)) return dev_err_probe(dev, PTR_ERR(base_regmap), @@ -1677,32 +1704,32 @@ static int k1_ccu_probe(struct platform_device *pdev) "failed to get lock regmap\n"); } - ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, - of_device_get_match_data(dev)); + ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data->clk); if (ret) return dev_err_probe(dev, ret, "failed to register clocks\n"); return 0; } +/* The match data is required to be non-null, and have a non-null clk pointer */ static const struct of_device_id of_k1_ccu_match[] = { { .compatible = "spacemit,k1-pll", - .data = k1_ccu_apbs_clks, + .data = &k1_ccu_apbs_data, }, { .compatible = "spacemit,k1-syscon-mpmu", - .data = k1_ccu_mpmu_clks, + .data = &k1_ccu_mpmu_data, }, { .compatible = "spacemit,k1-syscon-apbc", - .data = k1_ccu_apbc_clks, + .data = &k1_ccu_apbc_data, }, { .compatible = "spacemit,k1-syscon-apmu", - .data = k1_ccu_apmu_clks, + .data = &k1_ccu_apmu_data, }, - { } + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_k1_ccu_match); From patchwork Fri Mar 28 21:02:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 14032450 Received: from mail-il1-f179.google.com (mail-il1-f179.google.com [209.85.166.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D44251EF37C for ; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3d5d5a74286sm6769405ab.39.2025.03.28.14.02.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 14:02:41 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/7] clk: spacemit: add reset controller support Date: Fri, 28 Mar 2025 16:02:28 -0500 Message-ID: <20250328210233.1077035-4-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250328210233.1077035-1-elder@riscstar.com> References: <20250328210233.1077035-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Define ccu_reset_data as a structure that contains the constant register offset and bitmasks used to assert and deassert a reset control on a SpacemiT K1 CCU. Define ccu_reset_controller_data as a structure that contains the address of an array of those structures and a count of the number of elements in the array. Add a pointer to a ccu_reset_controller_data structure to the spacemit_ccu_data structure. Reset support is optional for SpacemiT CCUs; the new pointer field will be null for CCUs without any resets. Finally, define a new ccu_reset_controller structure, which (for a CCU with resets) contains a pointer to the constant reset data, the regmap to be used for the controller, and an embedded a reset controller structure. Each reset control is asserted or deasserted by updating bits in a register. The bits used are defined by an assert mask and a deassert mask. In some cases, one (non-zero) mask asserts reset and a different (non-zero) mask deasserts it. Otherwise one mask is nonzero, and the other is zero. Either way, the bits in both masks are cleared, then either the assert mask or the deassert mask is set in a register to affect the state of a reset control. Signed-off-by: Alex Elder --- v2: - Use regmap_update_bits() to safely update a register - Symbols are named RESET* and reset* rather than RST* and rst* - Reordered some assignments in the registration function - Allowed some longs to exceed 80 column width drivers/clk/spacemit/ccu-k1.c | 83 +++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 5cadb395a7dd6..9c7c7108cfe38 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "ccu_common.h" #include "ccu_pll.h" @@ -134,8 +135,26 @@ struct spacemit_ccu_clk { struct clk_hw *hw; }; +struct ccu_reset_data { + u32 offset; + u32 assert_mask; + u32 deassert_mask; +}; + +struct ccu_reset_controller_data { + u32 count; + const struct ccu_reset_data *data; /* array */ +}; + struct spacemit_ccu_data { struct spacemit_ccu_clk *clk; /* array with sentinel */ + const struct ccu_reset_controller_data *reset_data; +}; + +struct ccu_reset_controller { + struct regmap *regmap; + const struct ccu_reset_controller_data *data; + struct reset_controller_dev rcdev; }; /* APBS clocks start */ @@ -1630,6 +1649,39 @@ static const struct spacemit_ccu_data k1_ccu_apmu_data = { .clk = k1_ccu_apmu_clks, }; +static int spacemit_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct ccu_reset_controller *controller; + const struct ccu_reset_data *data; + u32 mask; + u32 val; + + controller = container_of(rcdev, struct ccu_reset_controller, rcdev); + data = &controller->data->data[id]; + mask = data->assert_mask | data->deassert_mask; + val = assert ? data->assert_mask : data->deassert_mask; + + return regmap_update_bits(controller->regmap, data->offset, mask, val); +} + +static int spacemit_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return spacemit_reset_update(rcdev, id, true); +} + +static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return spacemit_reset_update(rcdev, id, false); +} + +static const struct reset_control_ops spacemit_reset_control_ops = { + .assert = spacemit_reset_assert, + .deassert = spacemit_reset_deassert, +}; + static int spacemit_ccu_register(struct device *dev, struct regmap *regmap, struct regmap *lock_regmap, struct spacemit_ccu_clk *clks) @@ -1675,6 +1727,33 @@ static int spacemit_ccu_register(struct device *dev, return ret; } +static int spacemit_reset_controller_register(struct device *dev, + struct regmap *regmap, + const struct ccu_reset_controller_data *data) +{ + struct ccu_reset_controller *controller; + struct reset_controller_dev *rcdev; + + /* Resets are optional */ + if (!data) + return 0; + + controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); + if (!controller) + return -ENOMEM; + + controller->regmap = regmap; + controller->data = data; + + rcdev = &controller->rcdev; + rcdev->ops = &spacemit_reset_control_ops; + rcdev->owner = THIS_MODULE; + rcdev->of_node = dev->of_node; + rcdev->nr_resets = data->count; + + return devm_reset_controller_register(dev, rcdev); +} + static int k1_ccu_probe(struct platform_device *pdev) { struct regmap *base_regmap, *lock_regmap = NULL; @@ -1708,6 +1787,10 @@ static int k1_ccu_probe(struct platform_device *pdev) if (ret) return dev_err_probe(dev, ret, "failed to register clocks\n"); + ret = spacemit_reset_controller_register(dev, base_regmap, data->reset_data); + if (ret) + return dev_err_probe(dev, ret, "failed to register reset controller\n"); + return 0; } From patchwork Fri Mar 28 21:02:29 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 14032451 Received: from mail-il1-f178.google.com (mail-il1-f178.google.com [209.85.166.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A7291F17F7 for ; Fri, 28 Mar 2025 21:02:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.178 ARC-Seal: i=1; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3d5d5a74286sm6769405ab.39.2025.03.28.14.02.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 14:02:42 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/7] clk: spacemit: define existing syscon resets Date: Fri, 28 Mar 2025 16:02:29 -0500 Message-ID: <20250328210233.1077035-5-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250328210233.1077035-1-elder@riscstar.com> References: <20250328210233.1077035-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Define reset controls associated with the MPMU, APBC, and APMU SpacemiT K1 CCUs. These already have clocks associated with them. Signed-off-by: Alex Elder --- v2: - Symbols are named RESET* and reset* rather than RST* and rst* drivers/clk/spacemit/ccu-k1.c | 132 ++++++++++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 9c7c7108cfe38..f837d2c2f31fc 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -151,6 +151,13 @@ struct spacemit_ccu_data { const struct ccu_reset_controller_data *reset_data; }; +#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ + { \ + .offset = (_offset), \ + .assert_mask = (_assert_mask), \ + .deassert_mask = (_deassert_mask), \ + } + struct ccu_reset_controller { struct regmap *regmap; const struct ccu_reset_controller_data *data; @@ -1428,6 +1435,7 @@ static struct spacemit_ccu_clk k1_ccu_apbs_clks[] = { static const struct spacemit_ccu_data k1_ccu_apbs_data = { .clk = k1_ccu_apbs_clks, + /* No resets in the APBS CCU */ }; static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] = { @@ -1467,8 +1475,18 @@ static struct spacemit_ccu_clk k1_ccu_mpmu_clks[] = { { 0, NULL }, }; +static const struct ccu_reset_data mpmu_reset_data[] = { + [RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data mpmu_reset_controller_data = { + .count = ARRAY_SIZE(mpmu_reset_data), + .data = mpmu_reset_data, +}; + static const struct spacemit_ccu_data k1_ccu_mpmu_data = { .clk = k1_ccu_mpmu_clks, + .reset_data = &mpmu_reset_controller_data, }; static struct spacemit_ccu_clk k1_ccu_apbc_clks[] = { @@ -1575,8 +1593,68 @@ static struct spacemit_ccu_clk k1_ccu_apbc_clks[] = { { 0, NULL }, }; +static const struct ccu_reset_data apbc_reset_data[] = { + [RESET_UART0] = RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0), + [RESET_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), + [RESET_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), + [RESET_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)), + [RESET_SSP3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), + [RESET_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), + [RESET_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), + [RESET_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), + [RESET_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), + [RESET_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), + [RESET_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), + [RESET_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), + [RESET_SSPA0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), + [RESET_SSPA1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), + [RESET_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), + [RESET_IR] = RESET_DATA(APBC_IR_CLK_RST, BIT(2), 0), + [RESET_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), + [RESET_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), + [RESET_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), + [RESET_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), + [RESET_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), + [RESET_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), + [RESET_TWSI7] = RESET_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0), + [RESET_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), + [RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), + [RESET_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), + [RESET_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), + [RESET_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), + [RESET_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), + [RESET_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), + [RESET_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), + [RESET_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), +}; + +static const struct ccu_reset_controller_data apbc_reset_controller_data = { + .count = ARRAY_SIZE(apbc_reset_data), + .data = apbc_reset_data, +}; + static const struct spacemit_ccu_data k1_ccu_apbc_data = { .clk = k1_ccu_apbc_clks, + .reset_data = &apbc_reset_controller_data, }; static struct spacemit_ccu_clk k1_ccu_apmu_clks[] = { @@ -1645,8 +1723,62 @@ static struct spacemit_ccu_clk k1_ccu_apmu_clks[] = { { 0, NULL }, }; +static const struct ccu_reset_data apmu_reset_data[] = { + [RESET_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), + [RESET_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), + [RESET_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), + [RESET_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_USBP1_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)), + [RESET_USB_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), + [RESET_USB3_0] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(11) | BIT(10) | BIT(9)), + [RESET_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), + [RESET_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), + [RESET_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), + [RESET_AES] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), + [RESET_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), + [RESET_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMMC] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMMC_X] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)), + [RESET_AUDIO] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, + BIT(3) | BIT(2) | BIT(0)), + [RESET_HDMI] = RESET_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)), + [RESET_PCIE0] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_PCIE1] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_PCIE2] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_JPG] = RESET_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)), + [RESET_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), + [RESET_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), + [RESET_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_ISP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)), + [RESET_ISP_CPP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)), + [RESET_ISP_BUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)), + [RESET_ISP_CI] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), + [RESET_DPU_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), + [RESET_DPU_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), + [RESET_DPU_HCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), + [RESET_DPU_SPIBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)), + [RESET_DPU_SPI_HBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)), + [RESET_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), + [RESET_MIPI] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)), + [RESET_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), +}; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3d5d5a74286sm6769405ab.39.2025.03.28.14.02.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 14:02:44 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/7] clk: spacemit: make clocks optional Date: Fri, 28 Mar 2025 16:02:30 -0500 Message-ID: <20250328210233.1077035-6-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250328210233.1077035-1-elder@riscstar.com> References: <20250328210233.1077035-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There are some syscon devices that support both clocks and resets, but for now only their reset functionality is required. Make defining clocks optional for a SpacemiT CCU, though at least one clock or at least one reset controller must be defined. Signed-off-by: Alex Elder --- v2: - Comment explains constraints on match data drivers/clk/spacemit/ccu-k1.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index f837d2c2f31fc..6885fea81f6f3 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -1821,6 +1821,10 @@ static int spacemit_ccu_register(struct device *dev, const struct spacemit_ccu_clk *clk; int i, ret, max_id = 0; + /* Clocks are optional */ + if (!clks) + return 0; + for (clk = clks; clk->hw; clk++) max_id = max(max_id, clk->id); @@ -1926,7 +1930,7 @@ static int k1_ccu_probe(struct platform_device *pdev) return 0; } -/* The match data is required to be non-null, and have a non-null clk pointer */ +/* The match data is required, and its clk or reset_data field must not be null */ static const struct of_device_id of_k1_ccu_match[] = { { .compatible = "spacemit,k1-pll", From patchwork Fri Mar 28 21:02:31 2025 Content-Type: text/plain; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3d5d5a74286sm6769405ab.39.2025.03.28.14.02.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 14:02:45 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/7] clk: spacemit: define new syscons with only resets Date: Fri, 28 Mar 2025 16:02:31 -0500 Message-ID: <20250328210233.1077035-7-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250328210233.1077035-1-elder@riscstar.com> References: <20250328210233.1077035-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Enable support for three additional syscon CCUs which support reset controls but no clocks: ARCPU, RCPU2, and APBC2. Signed-off-by: Alex Elder --- v2: - Symbols are named RESET* and reset* rather than RST* and rst* drivers/clk/spacemit/ccu-k1.c | 106 ++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 6885fea81f6f3..c7c9580eab90b 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -130,6 +130,37 @@ #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec +/* RCPU register offsets */ +#define RCPU_SSP0_CLK_RST 0x0028 +#define RCPU_I2C0_CLK_RST 0x0030 +#define RCPU_UART1_CLK_RST 0x003c +#define RCPU_CAN_CLK_RST 0x0048 +#define RCPU_IR_CLK_RST 0x004c +#define RCPU_UART0_CLK_RST 0x00d8 +/* XXX Next one is part of the AUD_AUDCLOCK region @ 0xc0882000 */ +#define AUDIO_HDMI_CLK_CTRL 0x2044 + +/* RCPU2 register offsets */ +#define RCPU2_PWM0_CLK_RST 0x0000 +#define RCPU2_PWM1_CLK_RST 0x0004 +#define RCPU2_PWM2_CLK_RST 0x0008 +#define RCPU2_PWM3_CLK_RST 0x000c +#define RCPU2_PWM4_CLK_RST 0x0010 +#define RCPU2_PWM5_CLK_RST 0x0014 +#define RCPU2_PWM6_CLK_RST 0x0018 +#define RCPU2_PWM7_CLK_RST 0x001c +#define RCPU2_PWM8_CLK_RST 0x0020 +#define RCPU2_PWM9_CLK_RST 0x0024 + +/* APBC2 register offsets */ +#define APBC2_UART1_CLK_RST 0x0000 +#define APBC2_SSP2_CLK_RST 0x0004 +#define APBC2_TWSI3_CLK_RST 0x0008 +#define APBC2_RTC_CLK_RST 0x000c +#define APBC2_TIMERS0_CLK_RST 0x0010 +#define APBC2_KPC_CLK_RST 0x0014 +#define APBC2_GPIO_CLK_RST 0x001c + struct spacemit_ccu_clk { int id; struct clk_hw *hw; @@ -1781,6 +1812,69 @@ static const struct spacemit_ccu_data k1_ccu_apmu_data = { .reset_data = &apmu_reset_controller_data, }; +static const struct ccu_reset_data rcpu_reset_data[] = { + [RESET_RCPU_SSP0] = RESET_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_I2C0] = RESET_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_UART1] = RESET_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)), + [RESET_RCPU_IR] = RESET_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)), + [RESET_RCPU_CAN] = RESET_DATA(RCPU_IR_CLK_RST, 0, BIT(0)), + [RESET_RCPU_UART0] = RESET_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_HDMI_AUDIO] = RESET_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)), +}; + +static const struct ccu_reset_controller_data rcpu_reset_controller_data = { + .count = ARRAY_SIZE(rcpu_reset_data), + .data = rcpu_reset_data, +}; + +static struct spacemit_ccu_data k1_ccu_rcpu_data = { + /* No clocks in the RCPU CCU */ + .reset_data = &rcpu_reset_controller_data, +}; + +static const struct ccu_reset_data rcpu2_reset_data[] = { + [RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM9] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), +}; + +static const struct ccu_reset_controller_data rcpu2_reset_controller_data = { + .count = ARRAY_SIZE(rcpu2_reset_data), + .data = rcpu2_reset_data, +}; + +static struct spacemit_ccu_data k1_ccu_rcpu2_data = { + /* No clocks in the RCPU2 CCU */ + .reset_data = &rcpu2_reset_controller_data, +}; + +static const struct ccu_reset_data apbc2_reset_data[] = { + [RESET_APBC2_UART1] = RESET_DATA(APBC2_UART1_CLK_RST, BIT(2), (0)), + [RESET_APBC2_SSP2] = RESET_DATA(APBC2_SSP2_CLK_RST, BIT(2), (0)), + [RESET_APBC2_TWSI3] = RESET_DATA(APBC2_TWSI3_CLK_RST, BIT(2), (0)), + [RESET_APBC2_RTC] = RESET_DATA(APBC2_RTC_CLK_RST, BIT(2), (0)), + [RESET_APBC2_TIMERS0] = RESET_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), (0)), + [RESET_APBC2_KPC] = RESET_DATA(APBC2_KPC_CLK_RST, BIT(2), (0)), + [RESET_APBC2_GPIO] = RESET_DATA(APBC2_GPIO_CLK_RST, BIT(2), (0)), +}; + +static const struct ccu_reset_controller_data apbc2_reset_controller_data = { + .count = ARRAY_SIZE(apbc2_reset_data), + .data = apbc2_reset_data, +}; + +static struct spacemit_ccu_data k1_ccu_apbc2_data = { + /* No clocks in the APBC2 CCU */ + .reset_data = &apbc2_reset_controller_data, +}; + static int spacemit_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -1948,6 +2042,18 @@ static const struct of_device_id of_k1_ccu_match[] = { .compatible = "spacemit,k1-syscon-apmu", .data = &k1_ccu_apmu_data, }, + { + .compatible = "spacemit,k1-syscon-rcpu", + .data = &k1_ccu_rcpu_data, + }, + { + .compatible = "spacemit,k1-syscon-rcpu2", + .data = &k1_ccu_rcpu2_data, + }, + { + .compatible = "spacemit,k1-syscon-apbc2", + .data = &k1_ccu_apbc2_data, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, of_k1_ccu_match); From patchwork Fri Mar 28 21:02:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 14032454 Received: from mail-io1-f50.google.com (mail-io1-f50.google.com [209.85.166.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5ED31F418C for ; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-3d5d5a74286sm6769405ab.39.2025.03.28.14.02.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 14:02:47 -0700 (PDT) From: Alex Elder To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, dlan@gentoo.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/7] riscv: dts: spacemit: add reset support for the K1 SoC Date: Fri, 28 Mar 2025 16:02:32 -0500 Message-ID: <20250328210233.1077035-8-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250328210233.1077035-1-elder@riscstar.com> References: <20250328210233.1077035-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Define syscon nodes for the RCPU, RCPU2, and APBC2 SpacemiT CCUS, which currently support resets but not clocks in the SpacemiT K1. Signed-off-by: Alex Elder --- arch/riscv/boot/dts/spacemit/k1.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 09a9100986b19..f86d1b58c6d35 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -350,6 +350,18 @@ soc { dma-noncoherent; ranges; + syscon_rcpu: system-controller@c0880000 { + compatible = "spacemit,k1-syscon-rcpu"; + reg = <0x0 0xc0880000 0x0 0x2048>; + #reset-cells = <1>; + }; + + syscon_rcpu2: system-controller@c0888000 { + compatible = "spacemit,k1-syscon-rcpu2"; + reg = <0x0 0xc0888000 0x0 0x28>; + #reset-cells = <1>; + }; + syscon_apbc: system-control@d4015000 { compatible = "spacemit,k1-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>; @@ -518,6 +530,12 @@ clint: timer@e4000000 { <&cpu7_intc 3>, <&cpu7_intc 7>; }; + syscon_apbc2: system-controller@f0610000 { + compatible = "spacemit,k1-syscon-apbc2"; + reg = <0x0 0xf0610000 0x0 0x20>; + #reset-cells = <1>; + }; + sec_uart1: serial@f0612000 { compatible = "spacemit,k1-uart", "intel,xscale-uart"; reg = <0x0 0xf0612000 0x0 0x100>;