From patchwork Wed Apr 2 00:22:01 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 14035436 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91F0EC3601A for ; Wed, 2 Apr 2025 00:22:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9C3EC10E181; Wed, 2 Apr 2025 00:22:23 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="mM5QGsO1"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id DDA8F10E161; Wed, 2 Apr 2025 00:22:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743553340; x=1775089340; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FpXUSy/LNGFSEybZxd4bOaJ3PEd5kNAvQ5zUc9nCzOI=; b=mM5QGsO13v6QtxkW7lnqZov1/x8fi3bYfUDfldMaIKV2QyfoXHXPL+qN 8Ia2kDs9ygMbBOfUbB2jyceT8m9oFb0O2aDEItsFd5nwA7oyLDKLqtitS QOjeWzDg/1IgXvya63mBNmzheQbbmRYJHHTBtDb/hBz413sCtEs23YVvp G/isOipk/dIEtsJjCzVN4MnIkm6QQz55ALMCacO1HGzbJHHOmpESFW+Px ZhYcNi4JWRuwF2QhEByHAj8plo+z6o2TJiV912iAabIrqwKMDn96NBKIU iKBmASTOswNzWE1QcPq3oMndOUlj5wv1ZTv3k5SKpV51GmDrdmbbEeiLi A==; X-CSE-ConnectionGUID: mD2fhaSqSPqcNzY5kLhacA== X-CSE-MsgGUID: C+9KccKZSIyrZNvu9UN+mg== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="45021898" X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="45021898" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2025 17:22:16 -0700 X-CSE-ConnectionGUID: gM347V0ZQPKZaLTcUlcibg== X-CSE-MsgGUID: NO6VMTZ4Saygx30IC3QyCw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="131729576" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 01 Apr 2025 17:22:14 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 02 Apr 2025 03:22:12 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 1/9] drm/i915: Precompute plane SURF address Date: Wed, 2 Apr 2025 03:22:01 +0300 Message-ID: <20250402002209.24987-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250402002209.24987-1-ville.syrjala@linux.intel.com> References: <20250402002209.24987-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Currently we pre-compute the plane surface/base address partially (only for cursor_needs_physical cases) in intel_plane_pin_fb() and finish the calculation in the plane->update_arm(). Let's just precompute the whole thing instead. One benefit is that we get rid of all the vma offset stuff from the low level plane code. Another use I have in mind is including the surface address in the plane tracepoints, which should make it easier to analyze display faults. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 53 ++++++++++--------- drivers/gpu/drm/i915/display/i9xx_plane.h | 1 + drivers/gpu/drm/i915/display/intel_cursor.c | 18 +++---- .../drm/i915/display/intel_display_types.h | 5 +- drivers/gpu/drm/i915/display/intel_fb_pin.c | 27 ++++++---- .../drm/i915/display/intel_plane_initial.c | 2 + drivers/gpu/drm/i915/display/intel_sprite.c | 36 ++++++------- .../drm/i915/display/skl_universal_plane.c | 41 +++++++------- drivers/gpu/drm/xe/display/xe_fb_pin.c | 5 ++ drivers/gpu/drm/xe/display/xe_plane_initial.c | 4 ++ 10 files changed, 99 insertions(+), 93 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 5e8344fdfc28..bfeb4bf864e2 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -356,6 +356,19 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state, return 0; } +static u32 i8xx_plane_surf_offset(const struct intel_plane_state *plane_state) +{ + int x = plane_state->view.color_plane[0].x; + int y = plane_state->view.color_plane[0].y; + + return intel_fb_xy_to_linear(x, y, plane_state, 0); +} + +u32 i965_plane_surf_offset(const struct intel_plane_state *plane_state) +{ + return plane_state->view.color_plane[0].offset; +} + static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); @@ -459,7 +472,7 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; int x = plane_state->view.color_plane[0].x; int y = plane_state->view.color_plane[0].y; - u32 dspcntr, dspaddr_offset, linear_offset; + u32 dspcntr; dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); @@ -468,13 +481,6 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, crtc_state->async_flip_planes & BIT(plane->id)) dspcntr |= DISP_ASYNC_FLIP; - linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); - - if (DISPLAY_VER(display) >= 4) - dspaddr_offset = plane_state->view.color_plane[0].offset; - else - dspaddr_offset = linear_offset; - if (display->platform.cherryview && i9xx_plane == PLANE_B) { int crtc_x = plane_state->uapi.dst.x1; int crtc_y = plane_state->uapi.dst.y1; @@ -494,7 +500,7 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); } else if (DISPLAY_VER(display) >= 4) { intel_de_write_fw(display, DSPLINOFF(display, i9xx_plane), - linear_offset); + intel_fb_xy_to_linear(x, y, plane_state, 0)); intel_de_write_fw(display, DSPTILEOFF(display, i9xx_plane), DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); } @@ -507,11 +513,9 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); if (DISPLAY_VER(display) >= 4) - intel_de_write_fw(display, DSPSURF(display, i9xx_plane), - intel_plane_ggtt_offset(plane_state) + dspaddr_offset); + intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf); else - intel_de_write_fw(display, DSPADDR(display, i9xx_plane), - intel_plane_ggtt_offset(plane_state) + dspaddr_offset); + intel_de_write_fw(display, DSPADDR(display, i9xx_plane), plane_state->surf); } static void i830_plane_update_arm(struct intel_dsb *dsb, @@ -600,16 +604,13 @@ g4x_primary_async_flip(struct intel_dsb *dsb, { struct intel_display *display = to_intel_display(plane); u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); - u32 dspaddr_offset = plane_state->view.color_plane[0].offset; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; if (async_flip) dspcntr |= DISP_ASYNC_FLIP; intel_de_write_fw(display, DSPCNTR(display, i9xx_plane), dspcntr); - - intel_de_write_fw(display, DSPSURF(display, i9xx_plane), - intel_plane_ggtt_offset(plane_state) + dspaddr_offset); + intel_de_write_fw(display, DSPSURF(display, i9xx_plane), plane_state->surf); } static void @@ -620,11 +621,9 @@ vlv_primary_async_flip(struct intel_dsb *dsb, bool async_flip) { struct intel_display *display = to_intel_display(plane); - u32 dspaddr_offset = plane_state->view.color_plane[0].offset; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane), - intel_plane_ggtt_offset(plane_state) + dspaddr_offset); + intel_de_write_fw(display, DSPADDR_VLV(display, i9xx_plane), plane_state->surf); } static void @@ -1018,6 +1017,11 @@ intel_primary_plane_create(struct intel_display *display, enum pipe pipe) plane->get_hw_state = i9xx_plane_get_hw_state; plane->check_plane = i9xx_plane_check; + if (DISPLAY_VER(display) >= 4) + plane->surf_offset = i965_plane_surf_offset; + else + plane->surf_offset = i8xx_plane_surf_offset; + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) plane->capture_error = g4x_primary_capture_error; else if (DISPLAY_VER(display) >= 4) @@ -1233,24 +1237,21 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, const struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - u32 base; if (!plane_state->uapi.visible) return false; - base = intel_plane_ggtt_offset(plane_state); - /* * We may have moved the surface to a different * part of ggtt, make the plane aware of that. */ - if (plane_config->base == base) + if (plane_config->base == plane_state->surf) return false; if (DISPLAY_VER(display) >= 4) - intel_de_write(display, DSPSURF(display, i9xx_plane), base); + intel_de_write(display, DSPSURF(display, i9xx_plane), plane_state->surf); else - intel_de_write(display, DSPADDR(display, i9xx_plane), base); + intel_de_write(display, DSPADDR(display, i9xx_plane), plane_state->surf); return true; } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.h b/drivers/gpu/drm/i915/display/i9xx_plane.h index d90546d60855..565dab751301 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane.h @@ -24,6 +24,7 @@ unsigned int vlv_plane_min_alignment(struct intel_plane *plane, const struct drm_framebuffer *fb, int colot_plane); int i9xx_check_plane_surface(struct intel_plane_state *plane_state); +u32 i965_plane_surf_offset(const struct intel_plane_state *plane_state); struct intel_plane * intel_primary_plane_create(struct intel_display *display, enum pipe pipe); diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 3276a5b4a9b0..5333b34a5776 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -33,17 +33,9 @@ static const u32 intel_cursor_formats[] = { DRM_FORMAT_ARGB8888, }; -static u32 intel_cursor_base(const struct intel_plane_state *plane_state) +static u32 intel_cursor_surf_offset(const struct intel_plane_state *plane_state) { - struct intel_display *display = to_intel_display(plane_state); - u32 base; - - if (DISPLAY_INFO(display)->cursor_needs_physical) - base = plane_state->phys_dma_addr; - else - base = intel_plane_ggtt_offset(plane_state); - - return base + plane_state->view.color_plane[0].offset; + return plane_state->view.color_plane[0].offset; } static u32 intel_cursor_position(const struct intel_crtc_state *crtc_state, @@ -297,7 +289,7 @@ static void i845_cursor_update_arm(struct intel_dsb *dsb, size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width); - base = intel_cursor_base(plane_state); + base = plane_state->surf; pos = intel_cursor_position(crtc_state, plane_state, false); } @@ -675,7 +667,7 @@ static void i9xx_cursor_update_arm(struct intel_dsb *dsb, if (width != height) fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1); - base = intel_cursor_base(plane_state); + base = plane_state->surf; pos = intel_cursor_position(crtc_state, plane_state, false); } @@ -1051,6 +1043,8 @@ intel_cursor_plane_create(struct intel_display *display, cursor->check_plane = i9xx_check_cursor; } + cursor->surf_offset = intel_cursor_surf_offset; + if (DISPLAY_VER(display) >= 5 || display->platform.g4x) cursor->capture_error = g4x_cursor_capture_error; else diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 367b53a9eae2..0190eb33939e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -632,7 +632,6 @@ struct intel_plane_state { #define PLANE_HAS_FENCE BIT(0) struct intel_fb_view view; - u32 phys_dma_addr; /* for cursor_needs_physical */ /* for legacy cursor fb unpin */ struct drm_vblank_work unpin_work; @@ -655,6 +654,9 @@ struct intel_plane_state { /* chroma upsampler control register */ u32 cus_ctl; + /* surface address register */ + u32 surf; + /* * scaler_id * = -1 : not using a scaler @@ -1503,6 +1505,7 @@ struct intel_plane { bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe); int (*check_plane)(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state); + u32 (*surf_offset)(const struct intel_plane_state *plane_state); int (*min_cdclk)(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); void (*async_flip)(struct intel_dsb *dsb, diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index c648ab8a93d7..fb7d0c8b9302 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -276,17 +276,6 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, plane_state->ggtt_vma = vma; - /* - * Pre-populate the dma address before we enter the vblank - * evade critical section as i915_gem_object_get_dma_address() - * will trigger might_sleep() even if it won't actually sleep, - * which is the case when the fb has already been pinned. - */ - if (intel_plane_needs_physical(plane)) { - struct drm_i915_gem_object *obj = to_intel_bo(intel_fb_bo(&fb->base)); - - plane_state->phys_dma_addr = i915_gem_object_get_dma_address(obj, 0); - } } else { unsigned int alignment = intel_plane_fb_min_alignment(plane_state); @@ -310,6 +299,22 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma); } + /* + * Pre-populate the dma address before we enter the vblank + * evade critical section as i915_gem_object_get_dma_address() + * will trigger might_sleep() even if it won't actually sleep, + * which is the case when the fb has already been pinned. + */ + if (intel_plane_needs_physical(plane)) { + struct drm_i915_gem_object *obj = to_intel_bo(intel_fb_bo(&fb->base)); + + plane_state->surf = i915_gem_object_get_dma_address(obj, 0) + + plane->surf_offset(plane_state); + } else { + plane_state->surf = intel_plane_ggtt_offset(plane_state) + + plane->surf_offset(plane_state); + } + return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c index b0c4892775ce..1c49610eb42f 100644 --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c @@ -356,6 +356,8 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc, i915_vma_pin_fence(vma) == 0 && vma->fence) plane_state->flags |= PLANE_HAS_FENCE; + plane_state->surf = intel_plane_ggtt_offset(plane_state); + plane_state->uapi.src_x = 0; plane_state->uapi.src_y = 0; plane_state->uapi.src_w = fb->width << 16; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 1ad6c8a94b3d..9bcb8dda6129 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -394,15 +394,12 @@ vlv_sprite_update_arm(struct intel_dsb *dsb, enum pipe pipe = plane->pipe; enum plane_id plane_id = plane->id; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; - u32 sprsurf_offset = plane_state->view.color_plane[0].offset; u32 x = plane_state->view.color_plane[0].x; u32 y = plane_state->view.color_plane[0].y; - u32 sprctl, linear_offset; + u32 sprctl; sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state); - linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); - if (display->platform.cherryview && pipe == PIPE_B) chv_sprite_update_csc(plane_state); @@ -417,7 +414,8 @@ vlv_sprite_update_arm(struct intel_dsb *dsb, intel_de_write_fw(display, SPCONSTALPHA(pipe, plane_id), 0); - intel_de_write_fw(display, SPLINOFF(pipe, plane_id), linear_offset); + intel_de_write_fw(display, SPLINOFF(pipe, plane_id), + intel_fb_xy_to_linear(x, y, plane_state, 0)); intel_de_write_fw(display, SPTILEOFF(pipe, plane_id), SP_OFFSET_Y(y) | SP_OFFSET_X(x)); @@ -427,8 +425,7 @@ vlv_sprite_update_arm(struct intel_dsb *dsb, * the control register just before the surface register. */ intel_de_write_fw(display, SPCNTR(pipe, plane_id), sprctl); - intel_de_write_fw(display, SPSURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + sprsurf_offset); + intel_de_write_fw(display, SPSURF(pipe, plane_id), plane_state->surf); vlv_sprite_update_clrc(plane_state); vlv_sprite_update_gamma(plane_state); @@ -829,15 +826,12 @@ ivb_sprite_update_arm(struct intel_dsb *dsb, struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; - u32 sprsurf_offset = plane_state->view.color_plane[0].offset; u32 x = plane_state->view.color_plane[0].x; u32 y = plane_state->view.color_plane[0].y; - u32 sprctl, linear_offset; + u32 sprctl; sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state); - linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); - if (key->flags) { intel_de_write_fw(display, SPRKEYVAL(pipe), key->min_value); intel_de_write_fw(display, SPRKEYMSK(pipe), @@ -851,7 +845,8 @@ ivb_sprite_update_arm(struct intel_dsb *dsb, intel_de_write_fw(display, SPROFFSET(pipe), SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x)); } else { - intel_de_write_fw(display, SPRLINOFF(pipe), linear_offset); + intel_de_write_fw(display, SPRLINOFF(pipe), + intel_fb_xy_to_linear(x, y, plane_state, 0)); intel_de_write_fw(display, SPRTILEOFF(pipe), SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x)); } @@ -862,8 +857,7 @@ ivb_sprite_update_arm(struct intel_dsb *dsb, * the control register just before the surface register. */ intel_de_write_fw(display, SPRCTL(pipe), sprctl); - intel_de_write_fw(display, SPRSURF(pipe), - intel_plane_ggtt_offset(plane_state) + sprsurf_offset); + intel_de_write_fw(display, SPRSURF(pipe), plane_state->surf); ivb_sprite_update_gamma(plane_state); } @@ -1180,15 +1174,12 @@ g4x_sprite_update_arm(struct intel_dsb *dsb, struct intel_display *display = to_intel_display(plane); enum pipe pipe = plane->pipe; const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; - u32 dvssurf_offset = plane_state->view.color_plane[0].offset; u32 x = plane_state->view.color_plane[0].x; u32 y = plane_state->view.color_plane[0].y; - u32 dvscntr, linear_offset; + u32 dvscntr; dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state); - linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); - if (key->flags) { intel_de_write_fw(display, DVSKEYVAL(pipe), key->min_value); intel_de_write_fw(display, DVSKEYMSK(pipe), @@ -1196,7 +1187,8 @@ g4x_sprite_update_arm(struct intel_dsb *dsb, intel_de_write_fw(display, DVSKEYMAX(pipe), key->max_value); } - intel_de_write_fw(display, DVSLINOFF(pipe), linear_offset); + intel_de_write_fw(display, DVSLINOFF(pipe), + intel_fb_xy_to_linear(x, y, plane_state, 0)); intel_de_write_fw(display, DVSTILEOFF(pipe), DVS_OFFSET_Y(y) | DVS_OFFSET_X(x)); @@ -1206,8 +1198,7 @@ g4x_sprite_update_arm(struct intel_dsb *dsb, * the control register just before the surface register. */ intel_de_write_fw(display, DVSCNTR(pipe), dvscntr); - intel_de_write_fw(display, DVSSURF(pipe), - intel_plane_ggtt_offset(plane_state) + dvssurf_offset); + intel_de_write_fw(display, DVSSURF(pipe), plane_state->surf); if (display->platform.g4x) g4x_sprite_update_gamma(plane_state); @@ -1623,6 +1614,7 @@ intel_sprite_plane_create(struct intel_display *display, plane->capture_error = vlv_sprite_capture_error; plane->get_hw_state = vlv_sprite_get_hw_state; plane->check_plane = vlv_sprite_check; + plane->surf_offset = i965_plane_surf_offset; plane->max_stride = i965_plane_max_stride; plane->min_alignment = vlv_plane_min_alignment; plane->min_cdclk = vlv_plane_min_cdclk; @@ -1647,6 +1639,7 @@ intel_sprite_plane_create(struct intel_display *display, plane->capture_error = ivb_sprite_capture_error; plane->get_hw_state = ivb_sprite_get_hw_state; plane->check_plane = g4x_sprite_check; + plane->surf_offset = i965_plane_surf_offset; if (display->platform.broadwell || display->platform.haswell) { plane->max_stride = hsw_sprite_max_stride; @@ -1672,6 +1665,7 @@ intel_sprite_plane_create(struct intel_display *display, plane->capture_error = g4x_sprite_capture_error; plane->get_hw_state = g4x_sprite_get_hw_state; plane->check_plane = g4x_sprite_check; + plane->surf_offset = i965_plane_surf_offset; plane->max_stride = g4x_sprite_max_stride; plane->min_alignment = g4x_sprite_min_alignment; plane->min_cdclk = g4x_sprite_min_cdclk; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 8739195aba69..b82a9e07350b 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1285,13 +1285,20 @@ static u32 skl_surf_address(const struct intel_plane_state *plane_state, } } -static u32 skl_plane_surf(const struct intel_plane_state *plane_state, - int color_plane) +static int icl_plane_color_plane(const struct intel_plane_state *plane_state) { + if (plane_state->planar_linked_plane && !plane_state->is_y_plane) + return 1; + else + return 0; +} + +static u32 skl_plane_surf_offset(const struct intel_plane_state *plane_state) +{ + int color_plane = icl_plane_color_plane(plane_state); u32 plane_surf; - plane_surf = intel_plane_ggtt_offset(plane_state) + - skl_surf_address(plane_state, color_plane); + plane_surf = skl_surf_address(plane_state, color_plane); if (plane_state->decrypt) plane_surf |= PLANE_SURF_DECRYPT; @@ -1373,14 +1380,6 @@ static void icl_plane_csc_load_black(struct intel_dsb *dsb, intel_de_write_dsb(display, dsb, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0); } -static int icl_plane_color_plane(const struct intel_plane_state *plane_state) -{ - if (plane_state->planar_linked_plane && !plane_state->is_y_plane) - return 1; - else - return 0; -} - static void skl_plane_update_noarm(struct intel_dsb *dsb, struct intel_plane *plane, @@ -1476,7 +1475,7 @@ skl_plane_update_arm(struct intel_dsb *dsb, intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), plane_ctl); intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), - skl_plane_surf(plane_state, 0)); + plane_state->surf); } static void icl_plane_update_sel_fetch_noarm(struct intel_dsb *dsb, @@ -1632,7 +1631,6 @@ icl_plane_update_arm(struct intel_dsb *dsb, struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; - int color_plane = icl_plane_color_plane(plane_state); u32 plane_ctl; plane_ctl = plane_state->ctl | @@ -1658,7 +1656,7 @@ icl_plane_update_arm(struct intel_dsb *dsb, intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), plane_ctl); intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), - skl_plane_surf(plane_state, color_plane)); + plane_state->surf); } static void skl_plane_capture_error(struct intel_crtc *crtc, @@ -1682,10 +1680,10 @@ skl_plane_async_flip(struct intel_dsb *dsb, struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; - u32 plane_ctl = plane_state->ctl, plane_surf; + u32 plane_ctl = plane_state->ctl; + u32 plane_surf = plane_state->surf; plane_ctl |= skl_plane_ctl_crtc(crtc_state); - plane_surf = skl_plane_surf(plane_state, 0); if (async_flip) { if (DISPLAY_VER(display) >= 30) @@ -2837,6 +2835,8 @@ skl_universal_plane_create(struct intel_display *display, plane->min_cdclk = skl_plane_min_cdclk; } + plane->surf_offset = skl_plane_surf_offset; + if (DISPLAY_VER(display) >= 13) plane->max_stride = adl_plane_max_stride; else @@ -3163,21 +3163,18 @@ bool skl_fixup_initial_plane_config(struct intel_crtc *crtc, to_intel_plane_state(plane->base.state); enum plane_id plane_id = plane->id; enum pipe pipe = crtc->pipe; - u32 base; if (!plane_state->uapi.visible) return false; - base = intel_plane_ggtt_offset(plane_state); - /* * We may have moved the surface to a different * part of ggtt, make the plane aware of that. */ - if (plane_config->base == base) + if (plane_config->base == plane_state->surf) return false; - intel_de_write(display, PLANE_SURF(pipe, plane_id), base); + intel_de_write(display, PLANE_SURF(pipe, plane_id), plane_state->surf); return true; } diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index d918ae1c8061..b9c45a5a3d82 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -6,6 +6,7 @@ #include #include "i915_vma.h" +#include "intel_atomic_plane.h" #include "intel_display_types.h" #include "intel_dpt.h" #include "intel_fb.h" @@ -436,6 +437,10 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, return PTR_ERR(vma); new_plane_state->ggtt_vma = vma; + + new_plane_state->surf = intel_plane_ggtt_offset(new_plane_state) + + plane->surf_offset(new_plane_state); + return 0; } diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c index 4ca0cb571194..a15f60835239 100644 --- a/drivers/gpu/drm/xe/display/xe_plane_initial.c +++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c @@ -11,6 +11,7 @@ #include "xe_mmio.h" #include "i915_reg.h" +#include "i915_vma.h" #include "intel_atomic_plane.h" #include "intel_crtc.h" #include "intel_display.h" @@ -237,6 +238,9 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc, goto nofb; plane_state->ggtt_vma = vma; + + plane_state->surf = intel_plane_ggtt_offset(plane_state); + plane_state->uapi.src_x = 0; plane_state->uapi.src_y = 0; plane_state->uapi.src_w = fb->width << 16; From patchwork Wed Apr 2 00:22:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 14035434 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 759CCC36018 for ; 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X-CSE-ConnectionGUID: CIBDoLjcQaag7ICrJ9wNAg== X-CSE-MsgGUID: cVK3+L2cT9OYwgHn7WGxdw== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="45021901" X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="45021901" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2025 17:22:19 -0700 X-CSE-ConnectionGUID: my1U+ohbRvObTfhziH3EyQ== X-CSE-MsgGUID: w2cfXpx8Ri+j094lpQJSpg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="131729578" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 01 Apr 2025 17:22:17 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 02 Apr 2025 03:22:15 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 2/9] drm/i915: Nuke intel_plane_ggtt_offset() Date: Wed, 2 Apr 2025 03:22:02 +0300 Message-ID: <20250402002209.24987-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250402002209.24987-1-ville.syrjala@linux.intel.com> References: <20250402002209.24987-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We don't really need the extra intel_plane_ggtt_offset() wrapper anymore. Get rid of it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 5 ----- drivers/gpu/drm/i915/display/intel_atomic_plane.h | 2 -- drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +- drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +- drivers/gpu/drm/xe/display/xe_fb_pin.c | 2 +- drivers/gpu/drm/xe/display/xe_plane_initial.c | 2 +- 6 files changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 7276179df878..264a50b29c16 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -1565,8 +1565,3 @@ int intel_atomic_check_planes(struct intel_atomic_state *state) return 0; } - -u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state) -{ - return i915_ggtt_offset(plane_state->ggtt_vma); -} diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index 6efac923dcbc..65edd88d28a9 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -88,6 +88,4 @@ int intel_atomic_add_affected_planes(struct intel_atomic_state *state, struct intel_crtc *crtc); int intel_atomic_check_planes(struct intel_atomic_state *state); -u32 intel_plane_ggtt_offset(const struct intel_plane_state *plane_state); - #endif /* __INTEL_ATOMIC_PLANE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index fb7d0c8b9302..f2d8675dd98a 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -311,7 +311,7 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, plane_state->surf = i915_gem_object_get_dma_address(obj, 0) + plane->surf_offset(plane_state); } else { - plane_state->surf = intel_plane_ggtt_offset(plane_state) + + plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma) + plane->surf_offset(plane_state); } diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c index 1c49610eb42f..3afff528a7bd 100644 --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c @@ -356,7 +356,7 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc, i915_vma_pin_fence(vma) == 0 && vma->fence) plane_state->flags |= PLANE_HAS_FENCE; - plane_state->surf = intel_plane_ggtt_offset(plane_state); + plane_state->surf = i915_ggtt_offset(plane_state->ggtt_vma); plane_state->uapi.src_x = 0; plane_state->uapi.src_y = 0; diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index b9c45a5a3d82..b2e979805455 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -438,7 +438,7 @@ int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, new_plane_state->ggtt_vma = vma; - new_plane_state->surf = intel_plane_ggtt_offset(new_plane_state) + + new_plane_state->surf = i915_ggtt_offset(new_plane_state->ggtt_vma) + plane->surf_offset(new_plane_state); return 0; diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c index a15f60835239..c563edf14b1a 100644 --- a/drivers/gpu/drm/xe/display/xe_plane_initial.c +++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c @@ -239,7 +239,7 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc, plane_state->ggtt_vma = vma; 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a="45021916" X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="45021916" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2025 17:22:22 -0700 X-CSE-ConnectionGUID: T2GisVAeTM6fA45E0JmN0A== X-CSE-MsgGUID: nSZHZvTjTE+v0utEPxYk2Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="131729582" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 01 Apr 2025 17:22:20 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 02 Apr 2025 03:22:18 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 3/9] drm/i915: Move the intel_dpt_offset() check into intel_plane_pin_fb() Date: Wed, 2 Apr 2025 03:22:03 +0300 Message-ID: <20250402002209.24987-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250402002209.24987-1-ville.syrjala@linux.intel.com> References: <20250402002209.24987-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Now that we handle all the other vma offset stuff in intel_plane_pin_fb() it seems more proper to do the dpt_vma offset check there as well. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fb_pin.c | 7 +++++++ drivers/gpu/drm/i915/display/skl_universal_plane.c | 6 ------ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index f2d8675dd98a..a5b9d87b2255 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -259,6 +259,7 @@ intel_plane_fb_vtd_guard(const struct intel_plane_state *plane_state) int intel_plane_pin_fb(struct intel_plane_state *plane_state, const struct intel_plane_state *old_plane_state) { + struct intel_display *display = to_intel_display(plane_state); struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); @@ -297,6 +298,12 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, plane_state->dpt_vma = vma; WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma); + + /* + * The DPT object contains only one vma, so + * the VMA's offset within the DPT is always 0. + */ + drm_WARN_ON(display->drm, intel_dpt_offset(plane_state->dpt_vma)); } /* diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index b82a9e07350b..808580826b0e 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1271,12 +1271,6 @@ static u32 skl_surf_address(const struct intel_plane_state *plane_state, u32 offset = plane_state->view.color_plane[color_plane].offset; if (intel_fb_uses_dpt(fb)) { - /* - * The DPT object contains only one vma, so the VMA's offset - * within the DPT is always 0. - */ - drm_WARN_ON(display->drm, plane_state->dpt_vma && - intel_dpt_offset(plane_state->dpt_vma)); drm_WARN_ON(display->drm, offset & 0x1fffff); return offset >> 9; } else { From patchwork Wed Apr 2 00:22:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 14035435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 92934C3ABA0 for ; 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X-CSE-ConnectionGUID: hdV8XM4gTom5/QiGhqXFBQ== X-CSE-MsgGUID: VvfB2S0uRPCoMEuJfIalkA== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="45021929" X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="45021929" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2025 17:22:25 -0700 X-CSE-ConnectionGUID: J1+6tXKaRRKWbeh8ijwuJA== X-CSE-MsgGUID: TidmXsUUT9OSZKmsfOJBeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="131729585" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 01 Apr 2025 17:22:23 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 02 Apr 2025 03:22:22 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 4/9] drm/i915: Use i915_vma_offset() in intel_dpt_offset() Date: Wed, 2 Apr 2025 03:22:04 +0300 Message-ID: <20250402002209.24987-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250402002209.24987-1-ville.syrjala@linux.intel.com> References: <20250402002209.24987-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Replace the open coded vma mm node stuff in intel_dpt_offset() with i915_vma_offset(). This will also include the VT-d guard in the result. Granted that should always be 0 for DPT, but it seems prudent to include that in our DPT vma offset check anyway. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dpt.c | 2 +- drivers/gpu/drm/i915/display/intel_fb_pin.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c index 43bd97e4f589..2bf4ad6a0fdf 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt.c +++ b/drivers/gpu/drm/i915/display/intel_dpt.c @@ -321,5 +321,5 @@ void intel_dpt_destroy(struct i915_address_space *vm) u64 intel_dpt_offset(struct i915_vma *dpt_vma) { - return dpt_vma->node.start; + return i915_vma_offset(dpt_vma); } diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index a5b9d87b2255..d40e3d96b14a 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -300,8 +300,8 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state, WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma); /* - * The DPT object contains only one vma, so - * the VMA's offset within the DPT is always 0. + * The DPT object contains only one vma, and there is no VT-d + * guard, so the VMA's offset within the DPT is always 0. */ drm_WARN_ON(display->drm, intel_dpt_offset(plane_state->dpt_vma)); } From patchwork Wed Apr 2 00:22:05 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 14035437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3665FC3601E for ; Wed, 2 Apr 2025 00:22:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BF37B10E1ED; Wed, 2 Apr 2025 00:22:29 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="JBeSwFpd"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2EB6D10E1BB; Wed, 2 Apr 2025 00:22:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743553348; x=1775089348; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E13rsEPnFbn4439/YySIfXIwKK9qjUT2p/ffpxqtSOo=; b=JBeSwFpdpHobymRtPGRvxv77itBrW08EOfLajt/oGEdTECbVz+ZkIuD2 O71fqaapzxxT4JAinGBD/h6VxnE6INN9IB3Qo8lmFk5WvZ2kxq1hsm2o5 y9c57CVBdmzopcDj9BebvWfa6tayRPXb7O6z4WsCZTA3BV2GVeMeEeng0 23TInyvJ/5LT/9aF+mEEgy66yghUL/UWik1FsnH3N4aTPmwXDi0wDLpy7 mwE5teIqnbj0mL9OA4T4ISQdNPGYZt6ahunD2LPP0Bej3v9mrhXxHCpNF 8khZf/hxvPT3Zy/lLQaveR8ncFaC4dHjcjpg435E3/n+O2wfOAUONFc/4 A==; X-CSE-ConnectionGUID: WePpcMPWQKur4XWIiOTuHA== X-CSE-MsgGUID: AznnGE2cQ/Wu7ILTwNCvMg== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="45021940" X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="45021940" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2025 17:22:28 -0700 X-CSE-ConnectionGUID: vlGZ97u8TyaBzT06An9vkQ== X-CSE-MsgGUID: YSt5UhMyT2GbDrWjKPhILg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="131729586" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 01 Apr 2025 17:22:26 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 02 Apr 2025 03:22:25 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 5/9] drm/i915: Remove unused dpt_total_entries() Date: Wed, 2 Apr 2025 03:22:05 +0300 Message-ID: <20250402002209.24987-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250402002209.24987-1-ville.syrjala@linux.intel.com> References: <20250402002209.24987-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä dpt_total_entries() is not used anywhere. Remove it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dpt.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c index 2bf4ad6a0fdf..b505b52e93f8 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt.c +++ b/drivers/gpu/drm/i915/display/intel_dpt.c @@ -32,8 +32,6 @@ i915_vm_to_dpt(struct i915_address_space *vm) return container_of(vm, struct i915_dpt, vm); } -#define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT) - static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) { writeq(pte, addr); From patchwork Wed Apr 2 00:22:06 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 14035439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 634B4C3601C for ; Wed, 2 Apr 2025 00:22:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EB31110E695; Wed, 2 Apr 2025 00:22:32 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="esmjgXhy"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 44B0810E67A; Wed, 2 Apr 2025 00:22:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1743553351; x=1775089351; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZDTKX0RZroMNzNb3Vu/57mb3n7hIpcjkYddX+4ROLY4=; b=esmjgXhyLOn7qnfldqxc/rRkdKQPBpTovr9//Y+vv4AyUmrBaGWQGmer M3cip36mMokVhsBw/AZGTJkYPlT1dn/4/z/3uf7GgTVrzs9wBo7zwL72Q tnYADSILYRIoSJqxunVv+G2bH77ApYfbjJI/GwDV8APRbm7Or+sCURUpg YvM6j6DFLr8UEcOAxNSb4CFHguxp6Mnug4FTE211mF0uFaFNBZZk+sUmu Z68kT8vR/sTg3PlAJqMM9IoAtDtjGNHYpFwzZGXgKEgK6WrOef+q89uNk uGOJegf5b/dATTcz3F0aHZaj5xcZjdF8o6bVYfefx6XNzgGziezKtNjDL w==; X-CSE-ConnectionGUID: sYbcgoD+QpiKHcWwxqajGg== X-CSE-MsgGUID: OEuYwWW4RlyX+pNEmFc0Ug== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="45021948" X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="45021948" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2025 17:22:31 -0700 X-CSE-ConnectionGUID: 24yDRhaiR2W9rxvNzCNeZQ== X-CSE-MsgGUID: U7/47SBCSGqVwfYcZmwpJw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="131729588" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 01 Apr 2025 17:22:29 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 02 Apr 2025 03:22:28 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 6/9] drm/i915: Don't pass crtc_state to foo_plane_ctl() & co. Date: Wed, 2 Apr 2025 03:22:06 +0300 Message-ID: <20250402002209.24987-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250402002209.24987-1-ville.syrjala@linux.intel.com> References: <20250402002209.24987-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The *_plane_ctl() functions only consider the state of the plane (the state of the crtc is handled by the corresponding *_plane_ctl_crtc()), and thus they don't need the crtc_state at all. Don't pass it in. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 5 ++--- drivers/gpu/drm/i915/display/intel_cursor.c | 10 ++++------ drivers/gpu/drm/i915/display/intel_sprite.c | 15 ++++++--------- .../gpu/drm/i915/display/skl_universal_plane.c | 11 ++++------- 4 files changed, 16 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index bfeb4bf864e2..6a2609402431 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -151,8 +151,7 @@ static bool i9xx_plane_has_windowing(struct intel_plane *plane) i9xx_plane == PLANE_C; } -static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state) +static u32 i9xx_plane_ctl(const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; @@ -351,7 +350,7 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state, if (ret) return ret; - plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); + plane_state->ctl = i9xx_plane_ctl(plane_state); return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 5333b34a5776..8f9c8f0f4b27 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -205,8 +205,7 @@ static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) return cntl; } -static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state) +static u32 i845_cursor_ctl(const struct intel_plane_state *plane_state) { return CURSOR_ENABLE | CURSOR_FORMAT_ARGB | @@ -266,7 +265,7 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state, return -EINVAL; } - plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); + plane_state->ctl = i845_cursor_ctl(plane_state); return 0; } @@ -398,8 +397,7 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) return cntl; } -static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state) +static u32 i9xx_cursor_ctl(const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); u32 cntl = 0; @@ -526,7 +524,7 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, return -EINVAL; } - plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); + plane_state->ctl = i9xx_cursor_ctl(plane_state); return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 9bcb8dda6129..269065840b31 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -263,8 +263,7 @@ static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) return sprctl; } -static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state) +static u32 vlv_sprite_ctl(const struct intel_plane_state *plane_state) { const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; @@ -659,8 +658,7 @@ static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state) (display->platform.ivybridge || display->platform.haswell); } -static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state) +static u32 ivb_sprite_ctl(const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; @@ -1009,8 +1007,7 @@ static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) return dvscntr; } -static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state) +static u32 g4x_sprite_ctl(const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; @@ -1377,9 +1374,9 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state, return ret; if (DISPLAY_VER(display) >= 7) - plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state); + plane_state->ctl = ivb_sprite_ctl(plane_state); else - plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state); + plane_state->ctl = g4x_sprite_ctl(plane_state); return 0; } @@ -1429,7 +1426,7 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state, if (ret) return ret; - plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state); + plane_state->ctl = vlv_sprite_ctl(plane_state); return 0; } diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 808580826b0e..cc64d9598c17 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1166,8 +1166,7 @@ static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) return plane_ctl; } -static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state) +static u32 skl_plane_ctl(const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; @@ -1225,8 +1224,7 @@ static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) return plane_color_ctl; } -static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state) +static u32 glk_plane_color_ctl(const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); const struct drm_framebuffer *fb = plane_state->hw.fb; @@ -2355,11 +2353,10 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, plane_state->damage = DRM_RECT_INIT(0, 0, 0, 0); } - plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); + plane_state->ctl = skl_plane_ctl(plane_state); if (DISPLAY_VER(display) >= 10) - plane_state->color_ctl = glk_plane_color_ctl(crtc_state, - plane_state); + plane_state->color_ctl = glk_plane_color_ctl(plane_state); if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && icl_is_hdr_plane(display, plane->id)) From patchwork Wed Apr 2 00:22:07 2025 Content-Type: text/plain; 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d="scan'208";a="131729590" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 01 Apr 2025 17:22:32 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 02 Apr 2025 03:22:31 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 7/9] drm/i915: Include crtc contributed bits in plane_state->ctl Date: Wed, 2 Apr 2025 03:22:07 +0300 Message-ID: <20250402002209.24987-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250402002209.24987-1-ville.syrjala@linux.intel.com> References: <20250402002209.24987-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Currently we precompute plane_state->ctl with just the plane_state contributed bits, and the crtc contributed bits are added in ad-hoc fashion in all the places that write the plane control register. Clean this up by also including the crtc bits in the precomputed value. Technically the only place that needs the _ctl() vs. _ctl_crtc() split after this is i9xx_plane_disable_arm() (since we have to write the crtc bits even when disabling the plane), but I've opted to stick to the split on all platforms anyway. I think having clear areas of responsibility for each function is nice. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/i9xx_plane.c | 45 +++++++++---------- drivers/gpu/drm/i915/display/intel_cursor.c | 14 +++--- .../drm/i915/display/skl_universal_plane.c | 31 ++++--------- 3 files changed, 36 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 6a2609402431..ef830644bc44 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -151,6 +151,24 @@ static bool i9xx_plane_has_windowing(struct intel_plane *plane) i9xx_plane == PLANE_C; } +static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + u32 dspcntr = 0; + + if (crtc_state->gamma_enable) + dspcntr |= DISP_PIPE_GAMMA_ENABLE; + + if (crtc_state->csc_enable) + dspcntr |= DISP_PIPE_CSC_ENABLE; + + if (DISPLAY_VER(display) < 5) + dspcntr |= DISP_PIPE_SEL(crtc->pipe); + + return dspcntr; +} + static u32 i9xx_plane_ctl(const struct intel_plane_state *plane_state) { struct intel_display *display = to_intel_display(plane_state); @@ -350,7 +368,8 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state, if (ret) return ret; - plane_state->ctl = i9xx_plane_ctl(plane_state); + plane_state->ctl = i9xx_plane_ctl(plane_state) | + i9xx_plane_ctl_crtc(crtc_state); return 0; } @@ -368,24 +387,6 @@ u32 i965_plane_surf_offset(const struct intel_plane_state *plane_state) return plane_state->view.color_plane[0].offset; } -static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) -{ - struct intel_display *display = to_intel_display(crtc_state); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - u32 dspcntr = 0; - - if (crtc_state->gamma_enable) - dspcntr |= DISP_PIPE_GAMMA_ENABLE; - - if (crtc_state->csc_enable) - dspcntr |= DISP_PIPE_CSC_ENABLE; - - if (DISPLAY_VER(display) < 5) - dspcntr |= DISP_PIPE_SEL(crtc->pipe); - - return dspcntr; -} - static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state, unsigned int *num, unsigned int *den) @@ -471,9 +472,7 @@ static void i9xx_plane_update_arm(struct intel_dsb *dsb, enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; int x = plane_state->view.color_plane[0].x; int y = plane_state->view.color_plane[0].y; - u32 dspcntr; - - dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); + u32 dspcntr = plane_state->ctl; /* see intel_plane_atomic_calc_changes() */ if (plane->need_async_flip_toggle_wa && @@ -602,8 +601,8 @@ g4x_primary_async_flip(struct intel_dsb *dsb, bool async_flip) { struct intel_display *display = to_intel_display(plane); - u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; + u32 dspcntr = plane_state->ctl; if (async_flip) dspcntr |= DISP_ASYNC_FLIP; diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 8f9c8f0f4b27..debf0f9b7ff6 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -265,7 +265,8 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state, return -EINVAL; } - plane_state->ctl = i845_cursor_ctl(plane_state); + plane_state->ctl = i845_cursor_ctl(plane_state) | + i845_cursor_ctl_crtc(crtc_state); return 0; } @@ -283,11 +284,9 @@ static void i845_cursor_update_arm(struct intel_dsb *dsb, unsigned int width = drm_rect_width(&plane_state->uapi.dst); unsigned int height = drm_rect_height(&plane_state->uapi.dst); - cntl = plane_state->ctl | - i845_cursor_ctl_crtc(crtc_state); - size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width); + cntl = plane_state->ctl; base = plane_state->surf; pos = intel_cursor_position(crtc_state, plane_state, false); } @@ -524,7 +523,8 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, return -EINVAL; } - plane_state->ctl = i9xx_cursor_ctl(plane_state); + plane_state->ctl = i9xx_cursor_ctl(plane_state) | + i9xx_cursor_ctl_crtc(crtc_state); return 0; } @@ -659,12 +659,10 @@ static void i9xx_cursor_update_arm(struct intel_dsb *dsb, int width = drm_rect_width(&plane_state->uapi.dst); int height = drm_rect_height(&plane_state->uapi.dst); - cntl = plane_state->ctl | - i9xx_cursor_ctl_crtc(crtc_state); - if (width != height) fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1); + cntl = plane_state->ctl; base = plane_state->surf; pos = intel_cursor_position(crtc_state, plane_state, false); } diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index cc64d9598c17..2fd7cd76f804 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1414,20 +1414,13 @@ skl_plane_update_arm(struct intel_dsb *dsb, enum pipe pipe = plane->pipe; u32 x = plane_state->view.color_plane[0].x; u32 y = plane_state->view.color_plane[0].y; - u32 plane_ctl, plane_color_ctl = 0; - - plane_ctl = plane_state->ctl | - skl_plane_ctl_crtc(crtc_state); + u32 plane_ctl = plane_state->ctl; /* see intel_plane_atomic_calc_changes() */ if (plane->need_async_flip_toggle_wa && crtc_state->async_flip_planes & BIT(plane->id)) plane_ctl |= PLANE_CTL_ASYNC_FLIP; - if (DISPLAY_VER(display) >= 10) - plane_color_ctl = plane_state->color_ctl | - glk_plane_color_ctl_crtc(crtc_state); - intel_de_write_dsb(display, dsb, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state)); intel_de_write_dsb(display, dsb, PLANE_KEYMSK(pipe, plane_id), @@ -1447,7 +1440,7 @@ skl_plane_update_arm(struct intel_dsb *dsb, if (DISPLAY_VER(display) >= 10) intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id), - plane_color_ctl); + plane_state->color_ctl); /* * Enable the scaler before the plane so that we don't @@ -1534,10 +1527,6 @@ icl_plane_update_noarm(struct intel_dsb *dsb, int y = plane_state->view.color_plane[color_plane].y; int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; - u32 plane_color_ctl; - - plane_color_ctl = plane_state->color_ctl | - glk_plane_color_ctl_crtc(crtc_state); /* The scaler will handle the output position */ if (plane_state->scaler_id >= 0) { @@ -1579,7 +1568,7 @@ icl_plane_update_noarm(struct intel_dsb *dsb, plane_state->cus_ctl); intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id), - plane_color_ctl); + plane_state->color_ctl); if (fb->format->is_yuv && icl_is_hdr_plane(display, plane_id)) icl_program_input_csc(dsb, plane, plane_state); @@ -1623,10 +1612,6 @@ icl_plane_update_arm(struct intel_dsb *dsb, struct intel_display *display = to_intel_display(plane); enum plane_id plane_id = plane->id; enum pipe pipe = plane->pipe; - u32 plane_ctl; - - plane_ctl = plane_state->ctl | - skl_plane_ctl_crtc(crtc_state); /* * Enable the scaler before the plane so that we don't @@ -1646,7 +1631,7 @@ icl_plane_update_arm(struct intel_dsb *dsb, * the control register just before the surface register. */ intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), - plane_ctl); + plane_state->ctl); intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), plane_state->surf); } @@ -1675,8 +1660,6 @@ skl_plane_async_flip(struct intel_dsb *dsb, u32 plane_ctl = plane_state->ctl; u32 plane_surf = plane_state->surf; - plane_ctl |= skl_plane_ctl_crtc(crtc_state); - if (async_flip) { if (DISPLAY_VER(display) >= 30) plane_surf |= PLANE_SURF_ASYNC_UPDATE; @@ -2353,10 +2336,12 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, plane_state->damage = DRM_RECT_INIT(0, 0, 0, 0); } - plane_state->ctl = skl_plane_ctl(plane_state); + plane_state->ctl = skl_plane_ctl(plane_state) | + skl_plane_ctl_crtc(crtc_state); if (DISPLAY_VER(display) >= 10) - plane_state->color_ctl = glk_plane_color_ctl(plane_state); + plane_state->color_ctl = glk_plane_color_ctl(plane_state) | + glk_plane_color_ctl_crtc(crtc_state); if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && icl_is_hdr_plane(display, plane->id)) From patchwork Wed Apr 2 00:22:08 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 14035441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CDB97C3601A for ; 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X-CSE-ConnectionGUID: D3JaEDIFRieOQd2GodsmtA== X-CSE-MsgGUID: 57e3WEP0Ss+gZwpoEsf8vA== X-IronPort-AV: E=McAfee;i="6700,10204,11391"; a="45021964" X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="45021964" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2025 17:22:37 -0700 X-CSE-ConnectionGUID: 1wKsAfPQRee80uqaoqsCxg== X-CSE-MsgGUID: XxBqKu+BSg+OwtXbxdwAdg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,294,1736841600"; d="scan'208";a="131729597" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 01 Apr 2025 17:22:35 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 02 Apr 2025 03:22:34 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 8/9] drm/i915: Add tracepoint for plane faults Date: Wed, 2 Apr 2025 03:22:08 +0300 Message-ID: <20250402002209.24987-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250402002209.24987-1-ville.syrjala@linux.intel.com> References: <20250402002209.24987-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä When analying plane faults the exact sequence/timing of things can be important. Add a tracepoint for plane faults that can then be correclated against other tracepoints to figure out what happened and when. Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_display_irq.c | 2 ++ .../drm/i915/display/intel_display_trace.h | 33 +++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index d2a35e3630b1..d8bd06410542 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -87,6 +87,8 @@ static bool handle_plane_fault(struct intel_crtc *crtc, enum plane_id plane_id) plane->capture_error(crtc, plane, &error); + trace_intel_plane_fault(plane, crtc, error.ctl, error.surf, error.surflive); + drm_err_ratelimited(display->drm, "[CRTC:%d:%s][PLANE:%d:%s] fault (CTL=0x%x, SURF=0x%x, SURFLIVE=0x%x)\n", crtc->base.base.id, crtc->base.name, diff --git a/drivers/gpu/drm/i915/display/intel_display_trace.h b/drivers/gpu/drm/i915/display/intel_display_trace.h index 27ebc32cb61a..f0763d754eb7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_trace.h +++ b/drivers/gpu/drm/i915/display/intel_display_trace.h @@ -498,6 +498,39 @@ TRACE_EVENT(intel_plane_disable_arm, __entry->frame, __entry->scanline) ); +TRACE_EVENT(intel_plane_fault, + TP_PROTO(struct intel_plane *plane, struct intel_crtc *crtc, + u32 ctl, u32 surf, u32 surflive), + TP_ARGS(plane, crtc, ctl, surf, surflive), + + TP_STRUCT__entry( + __string(dev, __dev_name_kms(plane)) + __field(char, pipe_name) + __string(name, plane->base.name) + __field(u32, frame) + __field(u32, scanline) + __field(u32, ctl) + __field(u32, surf) + __field(u32, surflive) + ), + + TP_fast_assign( + __assign_str(dev); + __assign_str(name); + __entry->pipe_name = pipe_name(crtc->pipe); + __entry->frame = intel_crtc_get_vblank_counter(crtc); + __entry->scanline = intel_get_crtc_scanline(crtc); + __entry->ctl = ctl; + __entry->surf = surf; + __entry->surflive = surflive; + ), + + TP_printk("dev %s, pipe %c, %s, frame=%u, scanline=%u ctl=0x%x, surf=0x%x, surflive=0x%x", + __get_str(dev), __entry->pipe_name, __get_str(name), + __entry->frame, __entry->scanline, + __entry->ctl, __entry->surf, __entry->surflive) +); + TRACE_EVENT(intel_plane_scaler_update_arm, TP_PROTO(struct intel_plane *plane, int scaler_id, int x, int y, int w, int h), From patchwork Wed Apr 2 00:22:09 2025 Content-Type: text/plain; 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d="scan'208";a="131729607" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by orviesa005.jf.intel.com with SMTP; 01 Apr 2025 17:22:38 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 02 Apr 2025 03:22:37 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Subject: [PATCH 9/9] drm/i915: Include plane ctl/surf registers in the plane update_arm() tracepoint Date: Wed, 2 Apr 2025 03:22:09 +0300 Message-ID: <20250402002209.24987-10-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.45.3 In-Reply-To: <20250402002209.24987-1-ville.syrjala@linux.intel.com> References: <20250402002209.24987-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The plane fault tracepoints report the plane control and surface register values. In order to correlate those against the plane update tracepoints it might be helpful to also include that information in the plane update tracepoints as well. The one caveat here is that the precomputed ctl/surf values that we include the tracepoint do not include the async flip bit(s) (as those are handled in a more dynamic fashion), whereas the ones read from the hardware in the plane fault tracepoint include everything. Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_atomic_plane.c | 2 +- .../drm/i915/display/intel_display_trace.h | 28 +++++++++++++------ 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 264a50b29c16..24bb7ddbb06a 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -834,7 +834,7 @@ void intel_plane_async_flip(struct intel_dsb *dsb, { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - trace_intel_plane_async_flip(plane, crtc, async_flip); + trace_intel_plane_async_flip(plane_state, crtc, async_flip); plane->async_flip(dsb, plane, crtc_state, plane_state, async_flip); } diff --git a/drivers/gpu/drm/i915/display/intel_display_trace.h b/drivers/gpu/drm/i915/display/intel_display_trace.h index f0763d754eb7..91980567113d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_trace.h +++ b/drivers/gpu/drm/i915/display/intel_display_trace.h @@ -381,16 +381,19 @@ TRACE_EVENT(vlv_fifo_size, ); TRACE_EVENT(intel_plane_async_flip, - TP_PROTO(struct intel_plane *plane, struct intel_crtc *crtc, bool async_flip), - TP_ARGS(plane, crtc, async_flip), + TP_PROTO(const struct intel_plane_state *plane_state, + struct intel_crtc *crtc, bool async_flip), + TP_ARGS(plane_state, crtc, async_flip), TP_STRUCT__entry( - __string(dev, __dev_name_kms(plane)) + __string(dev, __dev_name_drm(plane_state->uapi.plane)) __field(char, pipe_name) __field(u32, frame) __field(u32, scanline) __field(bool, async_flip) - __string(name, plane->base.name) + __string(name, plane_state->uapi.plane->name) + __field(u32, ctl) + __field(u32, surf) ), TP_fast_assign( @@ -400,11 +403,15 @@ TRACE_EVENT(intel_plane_async_flip, __entry->frame = intel_crtc_get_vblank_counter(crtc); __entry->scanline = intel_get_crtc_scanline(crtc); __entry->async_flip = async_flip; + __entry->ctl = plane_state->ctl; + __entry->surf = plane_state->surf; ), - TP_printk("dev %s, pipe %c, %s, frame=%u, scanline=%u, async_flip=%s", + TP_printk("dev %s, pipe %c, %s, frame=%u, scanline=%u, async_flip=%s, ctl=0x%x, surf=0x%x", __get_str(dev), __entry->pipe_name, __get_str(name), - __entry->frame, __entry->scanline, str_yes_no(__entry->async_flip)) + __entry->frame, __entry->scanline, + str_yes_no(__entry->async_flip), + __entry->ctl, __entry->surf) ); TRACE_EVENT(intel_plane_update_noarm, @@ -453,6 +460,8 @@ TRACE_EVENT(intel_plane_update_arm, __array(int, src, 4) __array(int, dst, 4) __string(name, plane_state->uapi.plane->name) + __field(u32, ctl) + __field(u32, surf) ), TP_fast_assign( @@ -464,13 +473,16 @@ TRACE_EVENT(intel_plane_update_arm, __entry->format = plane_state->hw.fb->format->format; memcpy(__entry->src, &plane_state->uapi.src, sizeof(__entry->src)); memcpy(__entry->dst, &plane_state->uapi.dst, sizeof(__entry->dst)); + __entry->ctl = plane_state->ctl; + __entry->surf = plane_state->surf; ), - TP_printk("dev %s, pipe %c, %s, frame=%u, scanline=%u, format=%p4cc, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT, + TP_printk("dev %s, pipe %c, %s, frame=%u, scanline=%u, format=%p4cc, " DRM_RECT_FP_FMT " -> " DRM_RECT_FMT " ctl=0x%x, surf=0x%x", __get_str(dev), __entry->pipe_name, __get_str(name), __entry->frame, __entry->scanline, &__entry->format, DRM_RECT_FP_ARG((const struct drm_rect *)__entry->src), - DRM_RECT_ARG((const struct drm_rect *)__entry->dst)) + DRM_RECT_ARG((const struct drm_rect *)__entry->dst), + __entry->ctl, __entry->surf) ); TRACE_EVENT(intel_plane_disable_arm,