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This can lead to race conditions when multiple CPUs attempt to enable or disable the CATU device simultaneously. To address these race conditions, this patch introduces the following changes: 1. The enable and disable operations for the CATU device are not reentrant. Therefore, a spinlock is added to ensure that only one CPU can enable or disable a given CATU device at any point in time. 2. A reference counter is used to manage the enable/disable state of the CATU device. The device is enabled when the first CPU requires it and is only disabled when the last CPU finishes using it. This ensures the device remains active as long as at least one CPU needs it. Signed-off-by: Yabin Cui --- drivers/hwtracing/coresight/coresight-catu.c | 27 ++++++++++++++------ drivers/hwtracing/coresight/coresight-catu.h | 1 + 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index fa170c966bc3..b1d490dd7249 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -458,12 +458,17 @@ static int catu_enable_hw(struct catu_drvdata *drvdata, enum cs_mode cs_mode, static int catu_enable(struct coresight_device *csdev, enum cs_mode mode, void *data) { - int rc; + int rc = 0; struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev); + guard(raw_spinlock_irqsave)(&catu_drvdata->spinlock); - CS_UNLOCK(catu_drvdata->base); - rc = catu_enable_hw(catu_drvdata, mode, data); - CS_LOCK(catu_drvdata->base); + if (csdev->refcnt == 0) { + CS_UNLOCK(catu_drvdata->base); + rc = catu_enable_hw(catu_drvdata, mode, data); + CS_LOCK(catu_drvdata->base); + } + if (!rc) + csdev->refcnt++; return rc; } @@ -486,12 +491,17 @@ static int catu_disable_hw(struct catu_drvdata *drvdata) static int catu_disable(struct coresight_device *csdev, void *__unused) { - int rc; + int rc = 0; struct catu_drvdata *catu_drvdata = csdev_to_catu_drvdata(csdev); + guard(raw_spinlock_irqsave)(&catu_drvdata->spinlock); - CS_UNLOCK(catu_drvdata->base); - rc = catu_disable_hw(catu_drvdata); - CS_LOCK(catu_drvdata->base); + if (--csdev->refcnt == 0) { + CS_UNLOCK(catu_drvdata->base); + rc = catu_disable_hw(catu_drvdata); + CS_LOCK(catu_drvdata->base); + } else { + rc = -EBUSY; + } return rc; } @@ -550,6 +560,7 @@ static int __catu_probe(struct device *dev, struct resource *res) dev->platform_data = pdata; drvdata->base = base; + raw_spin_lock_init(&drvdata->spinlock); catu_desc.access = CSDEV_ACCESS_IOMEM(base); catu_desc.pdata = pdata; catu_desc.dev = dev; diff --git a/drivers/hwtracing/coresight/coresight-catu.h b/drivers/hwtracing/coresight/coresight-catu.h index 141feac1c14b..755776cd19c5 100644 --- a/drivers/hwtracing/coresight/coresight-catu.h +++ b/drivers/hwtracing/coresight/coresight-catu.h @@ -65,6 +65,7 @@ struct catu_drvdata { void __iomem *base; struct coresight_device *csdev; int irq; + raw_spinlock_t spinlock; }; #define CATU_REG32(name, offset) \ From patchwork Wed Apr 2 01:18:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yabin Cui X-Patchwork-Id: 14035476 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C9ABEC36010 for ; Wed, 2 Apr 2025 01:24:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:Cc:To:From: Subject:Message-ID:References:Mime-Version:In-Reply-To:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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AJvYcCXDbaqrVwmfa5BD4egwJUNXvTtlR+lF0RDT8bOygoTSUC9W+lrelCWP66SY3L1lWqfIl844XjOm+PuqutxV587/@lists.infradead.org X-Gm-Message-State: AOJu0Yww8FWQy6zJ4AmQ8MJyYOiIrYTlJ8iFuC+p9MBy/+7sQww7EIJj aFSzJQpMQU5zXVNQ545pAFRx7ZdKuBMFU8uvl4irVTJm0f0Am/yE5AVKGg9K0oqOk9e2/KWRNkB 9 X-Google-Smtp-Source: AGHT+IF2odUx6KL5NWFPqm5G8r/6pPbHDFTjru8tv1QaI+AKSymC55lai62Y/Vh/TzF1U2eaSauiAA7d+M0= X-Received: from pjbpl10.prod.google.com ([2002:a17:90b:268a:b0:2fa:15aa:4d1e]) (user=yabinc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:538f:b0:2ea:8aac:6ac1 with SMTP id 98e67ed59e1d1-30572609c09mr225709a91.15.1743556781014; Tue, 01 Apr 2025 18:19:41 -0700 (PDT) Date: Tue, 1 Apr 2025 18:18:31 -0700 In-Reply-To: <20250402011832.2970072-1-yabinc@google.com> Mime-Version: 1.0 References: <20250402011832.2970072-1-yabinc@google.com> X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog Message-ID: <20250402011832.2970072-3-yabinc@google.com> Subject: [PATCH v2 2/3] coresight: catu: Prevent concurrent PERF and SYSFS mode enablement From: Yabin Cui To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yabin Cui , Leo Yan X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250401_181942_370962_556777CD X-CRM114-Status: GOOD ( 15.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A CATU device can be enabled for either PERF mode or SYSFS mode, but not both simultaneously. Consider the following race condition: CPU 1 enables CATU for PERF mode. CPU 2 enables CATU for SYSFS mode. It only increases refcnt. CPU 2 enables ETR for SYSFS mode. CPU 1 fails to enable ETR for PERF mode. This results in a CATU being enabled in PERF mode and an ETR enabled in SYSFS mode, leading to unknown behavior. To prevent this situation, this patch checks enabled mode of a CATU device before increasing its refcnt. Signed-off-by: Yabin Cui Suggested-by: James Clark Suggested-by: Leo Yan --- drivers/hwtracing/coresight/coresight-catu.c | 6 +++++- drivers/hwtracing/coresight/coresight-catu.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c index b1d490dd7249..0caf3a3e75ce 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -466,7 +466,10 @@ static int catu_enable(struct coresight_device *csdev, enum cs_mode mode, CS_UNLOCK(catu_drvdata->base); rc = catu_enable_hw(catu_drvdata, mode, data); CS_LOCK(catu_drvdata->base); - } + if (!rc) + catu_drvdata->mode = mode; + } else if (catu_drvdata->mode != mode) + rc = -EBUSY; if (!rc) csdev->refcnt++; return rc; @@ -499,6 +502,7 @@ static int catu_disable(struct coresight_device *csdev, void *__unused) CS_UNLOCK(catu_drvdata->base); rc = catu_disable_hw(catu_drvdata); CS_LOCK(catu_drvdata->base); + catu_drvdata->mode = CS_MODE_DISABLED; } else { rc = -EBUSY; } diff --git a/drivers/hwtracing/coresight/coresight-catu.h b/drivers/hwtracing/coresight/coresight-catu.h index 755776cd19c5..ea406464f0a8 100644 --- a/drivers/hwtracing/coresight/coresight-catu.h +++ b/drivers/hwtracing/coresight/coresight-catu.h @@ -66,6 +66,7 @@ struct catu_drvdata { struct coresight_device *csdev; int irq; raw_spinlock_t spinlock; + enum cs_mode mode; }; #define CATU_REG32(name, offset) \ From patchwork Wed Apr 2 01:18:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yabin Cui X-Patchwork-Id: 14035477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56EE0C36010 for ; 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Tue, 01 Apr 2025 18:19:47 -0700 (PDT) Date: Tue, 1 Apr 2025 18:18:32 -0700 In-Reply-To: <20250402011832.2970072-1-yabinc@google.com> Mime-Version: 1.0 References: <20250402011832.2970072-1-yabinc@google.com> X-Mailer: git-send-email 2.49.0.472.ge94155a9ec-goog Message-ID: <20250402011832.2970072-4-yabinc@google.com> Subject: [PATCH v2 3/3] coresight: core: Disable helpers for devices that fail to enable From: Yabin Cui To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Yabin Cui X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250401_181948_113898_950A5273 X-CRM114-Status: GOOD ( 14.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When enabling a SINK or LINK type coresight device fails, the associated helpers should be disabled. Signed-off-by: Yabin Cui Suggested-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-core.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index fb43ef6a3b1f..e3270d9b46c9 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -465,7 +465,7 @@ int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, /* Enable all helpers adjacent to the path first */ ret = coresight_enable_helpers(csdev, mode, path); if (ret) - goto err; + goto err_helper; /* * ETF devices are tricky... They can be a link or a sink, * depending on how they are configured. If an ETF has been @@ -480,14 +480,8 @@ int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, switch (type) { case CORESIGHT_DEV_TYPE_SINK: ret = coresight_enable_sink(csdev, mode, sink_data); - /* - * Sink is the first component turned on. If we - * failed to enable the sink, there are no components - * that need disabling. Disabling the path here - * would mean we could disrupt an existing session. - */ if (ret) - goto out; + goto err; break; case CORESIGHT_DEV_TYPE_SOURCE: /* sources are enabled from either sysFS or Perf */ @@ -507,6 +501,8 @@ int coresight_enable_path(struct coresight_path *path, enum cs_mode mode, out: return ret; err: + coresight_disable_helpers(csdev); +err_helper: coresight_disable_path_from(path, nd); goto out; }