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Wed, 2 Apr 2025 13:12:33 +0000 From: Tommaso Merciai To: tomm.merciai@gmail.com Cc: linux-renesas-soc@vger.kernel.org, biju.das.jz@bp.renesas.com, Tommaso Merciai , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] clk: renesas: r9a09g047: Add clock and reset entries for GE3D Date: Wed, 2 Apr 2025 15:11:38 +0200 Message-ID: <20250402131142.1270701-2-tommaso.merciai.xr@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250402131142.1270701-1-tommaso.merciai.xr@bp.renesas.com> References: <20250402131142.1270701-1-tommaso.merciai.xr@bp.renesas.com> X-ClientProxiedBy: FR4P281CA0173.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:b7::16) To OS9PR01MB13950.jpnprd01.prod.outlook.com (2603:1096:604:35e::5) Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OS9PR01MB13950:EE_|TYCPR01MB6688:EE_ X-MS-Office365-Filtering-Correlation-Id: c5c6145d-3daf-4993-3b55-08dd71e80778 X-LD-Processed: 53d82571-da19-47e4-9cb4-625a166a4a2a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|52116014|1800799024|366016|38350700014; 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Signed-off-by: Tommaso Merciai --- drivers/clk/renesas/r9a09g047-cpg.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c index e9cf4342d0cfb..2aa1e0aa4d36d 100644 --- a/drivers/clk/renesas/r9a09g047-cpg.c +++ b/drivers/clk/renesas/r9a09g047-cpg.c @@ -41,6 +41,7 @@ enum clk_ids { CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_DIV16, CLK_PLLVDO_CRU0, + CLK_PLLVDO_GPU, /* Module Clocks */ MOD_CLK_BASE, @@ -96,6 +97,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), + DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64), /* Core Clocks */ DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1), @@ -185,6 +187,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { BUS_MSTOP(9, BIT(4))), DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10, BUS_MSTOP(2, BIT(15))), + DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16, + BUS_MSTOP(3, BIT(4))), + DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17, + BUS_MSTOP(3, BIT(4))), + DEF_MOD("ge3d_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, + BUS_MSTOP(3, BIT(4))), }; static const struct rzv2h_reset r9a09g047_resets[] __initconst = { @@ -214,6 +222,9 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */ + DEF_RST(13, 13, 6, 14), /* GE3D_0_RESETN */ + DEF_RST(13, 14, 6, 15), /* GE3D_0_AXI_RESETN */ + DEF_RST(13, 15, 6, 16), /* GE3D_0_ACE_RESETN */ }; const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = { From patchwork Wed Apr 2 13:11:39 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tommaso Merciai X-Patchwork-Id: 14035990 X-Patchwork-Delegate: geert@linux-m68k.org Received: from TYVP286CU001.outbound.protection.outlook.com (mail-japaneastazon11011053.outbound.protection.outlook.com [52.101.125.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87157238D50; 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These variants share the same restrictions on interrupts, clocks, and power domains as the RZ/G2L SoC, so extend the existing schema validation accordingly. Signed-off-by: Tommaso Merciai --- Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 019bd28a29f19..e25478f2ce521 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -25,6 +25,7 @@ properties: - realtek,rtd1619-mali - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a09g047-mali - renesas,r9a09g057-mali - rockchip,px30-mali - rockchip,rk3562-mali @@ -145,6 +146,7 @@ allOf: enum: - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a09g047-mali - renesas,r9a09g057-mali then: properties: From patchwork Wed Apr 2 13:11:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tommaso Merciai X-Patchwork-Id: 14035991 X-Patchwork-Delegate: geert@linux-m68k.org Received: from OS0P286CU011.outbound.protection.outlook.com (mail-japanwestazon11010055.outbound.protection.outlook.com [52.101.228.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB610238D50; 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Signed-off-by: Tommaso Merciai --- arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi index 4bc0b77f721ab..9ab83e949c0ea 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi @@ -105,6 +105,35 @@ L3_CA55: cache-controller-0 { }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000>; + opp-microvolt = <800000>; + }; + + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-microvolt = <800000>; + }; + + opp-157500000 { + opp-hz = /bits/ 64 <157500000>; + opp-microvolt = <800000>; + }; + + opp-78750000 { + opp-hz = /bits/ 64 <78750000>; + opp-microvolt = <800000>; + }; + + opp-19687500 { + opp-hz = /bits/ 64 <19687500>; + opp-microvolt = <800000>; + }; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -491,6 +520,26 @@ i2c8: i2c@11c01000 { status = "disabled"; }; + gpu: gpu@14850000 { + compatible = "renesas,r9a09g047-mali", + "arm,mali-bifrost"; + reg = <0x0 0x14850000 0x0 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "job", "mmu", "gpu", "event"; + clocks = <&cpg CPG_MOD 0xf0>, + <&cpg CPG_MOD 0xf1>, + <&cpg CPG_MOD 0xf2>; + clock-names = "gpu", "bus", "bus_ace"; + power-domains = <&cpg>; + resets = <&cpg 0xdd>, <&cpg 0xde>, <&cpg 0xdf>; + reset-names = "rst", "axi_rst", "ace_rst"; + operating-points-v2 = <&gpu_opp_table>; + status = "disabled"; + }; + gic: interrupt-controller@14900000 { compatible = "arm,gic-v3"; reg = <0x0 0x14900000 0 0x20000>, From patchwork Wed Apr 2 13:11:41 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tommaso Merciai X-Patchwork-Id: 14035999 X-Patchwork-Delegate: geert@linux-m68k.org Received: from OS0P286CU011.outbound.protection.outlook.com (mail-japanwestazon11010007.outbound.protection.outlook.com [52.101.228.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5490C238D50; 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Signed-off-by: Tommaso Merciai --- arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi index 72b42a81bcf34..5c4596dea2160 100644 --- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi @@ -45,6 +45,16 @@ reg_3p3v: regulator-3p3v { regulator-boot-on; regulator-always-on; }; + + reg_vdd0p8v_others: regulator-vdd0p8v-others { + compatible = "regulator-fixed"; + + regulator-name = "fixed-0.8V"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; }; &audio_extal_clk { @@ -123,6 +133,11 @@ sd2-pwen { }; }; +&gpu { + status = "okay"; + mali-supply = <®_vdd0p8v_others>; +}; + &qextal_clk { clock-frequency = <24000000>; };