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The capability layout is the same as PCI_EXT_CAP_ID_REBAR. Add the capability ID and restore it as a part of IOV state. See PCIe r6.2, sec 7.8.7. Signed-off-by: Michał Winiarski Reviewed-by: Ilpo Järvinen Reviewed-by: Christian König --- drivers/pci/iov.c | 30 +++++++++++++++++++++++++++++- drivers/pci/pci.h | 1 + include/uapi/linux/pci_regs.h | 9 +++++++++ 3 files changed, 39 insertions(+), 1 deletion(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 10693b5d7eb66..8bdc0829f847b 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -7,6 +7,7 @@ * Copyright (C) 2009 Intel Corporation, Yu Zhao */ +#include #include #include #include @@ -850,6 +851,7 @@ static int sriov_init(struct pci_dev *dev, int pos) pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link); if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) iov->link = PCI_DEVFN(PCI_SLOT(dev->devfn), iov->link); + iov->vf_rebar_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VF_REBAR); if (pdev) iov->dev = pci_dev_get(pdev); @@ -888,6 +890,30 @@ static void sriov_release(struct pci_dev *dev) dev->sriov = NULL; } +static void sriov_restore_vf_rebar_state(struct pci_dev *dev) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + pos = dev->sriov->vf_rebar_cap; + if (!pos) + return; + + pci_read_config_dword(dev, pos + PCI_VF_REBAR_CTRL, &ctrl); + nbars = FIELD_GET(PCI_VF_REBAR_CTRL_NBAR_MASK, ctrl); + + for (i = 0; i < nbars; i++, pos += 8) { + int bar_idx, size; + + pci_read_config_dword(dev, pos + PCI_VF_REBAR_CTRL, &ctrl); + bar_idx = FIELD_GET(PCI_VF_REBAR_CTRL_BAR_IDX, ctrl); + size = pci_rebar_bytes_to_size(dev->sriov->barsz[bar_idx]); + ctrl &= ~PCI_VF_REBAR_CTRL_BAR_SIZE; + ctrl |= FIELD_PREP(PCI_VF_REBAR_CTRL_BAR_SIZE, size); + pci_write_config_dword(dev, pos + PCI_VF_REBAR_CTRL, ctrl); + } +} + static void sriov_restore_state(struct pci_dev *dev) { int i; @@ -1047,8 +1073,10 @@ resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno) */ void pci_restore_iov_state(struct pci_dev *dev) { - if (dev->is_physfn) + if (dev->is_physfn) { + sriov_restore_vf_rebar_state(dev); sriov_restore_state(dev); + } } /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index b81e99cd4b62a..adc54bb2c8b34 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -482,6 +482,7 @@ struct pci_sriov { u16 subsystem_vendor; /* VF subsystem vendor */ u16 subsystem_device; /* VF subsystem device */ resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ + u16 vf_rebar_cap; /* VF Resizable BAR capability offset */ bool drivers_autoprobe; /* Auto probing of VFs by driver */ }; diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index ba326710f9c8b..b2d5f3ac79ae9 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -745,6 +745,7 @@ #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ +#define PCI_EXT_CAP_ID_VF_REBAR 0x24 /* VF Resizable BAR */ #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ @@ -1140,6 +1141,14 @@ #define PCI_DVSEC_HEADER2 0x8 /* Designated Vendor-Specific Header2 */ #define PCI_DVSEC_HEADER2_ID(x) ((x) & 0xffff) +/* VF Resizable BARs, same layout as PCI_REBAR */ +#define PCI_VF_REBAR_CAP PCI_REBAR_CAP +#define PCI_VF_REBAR_CAP_SIZES PCI_REBAR_CAP_SIZES +#define PCI_VF_REBAR_CTRL PCI_REBAR_CTRL +#define PCI_VF_REBAR_CTRL_BAR_IDX PCI_REBAR_CTRL_BAR_IDX +#define PCI_VF_REBAR_CTRL_NBAR_MASK PCI_REBAR_CTRL_NBAR_MASK +#define PCI_VF_REBAR_CTRL_BAR_SIZE PCI_REBAR_CTRL_BAR_SIZE + /* Data Link Feature */ #define PCI_DLF_CAP 0x04 /* Capabilities Register */ #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ From patchwork Wed Apr 2 14:11:18 2025 Content-Type: text/plain; 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Extract the logic to pci_resource_num_from_vf_bar() and pci_resource_num_to_vf_bar() helpers. Suggested-by: Ilpo Järvinen Signed-off-by: Michał Winiarski Acked-by: Christian König Reviewed-by: Ilpo Järvinen --- drivers/pci/iov.c | 26 ++++++++++++++++---------- drivers/pci/pci.h | 19 +++++++++++++++++++ drivers/pci/setup-bus.c | 3 ++- 3 files changed, 37 insertions(+), 11 deletions(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 8bdc0829f847b..3d5da055c3dc1 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -151,7 +151,7 @@ resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) if (!dev->is_physfn) return 0; - return dev->sriov->barsz[resno - PCI_IOV_RESOURCES]; + return dev->sriov->barsz[pci_resource_num_to_vf_bar(resno)]; } static void pci_read_vf_config_common(struct pci_dev *virtfn) @@ -342,12 +342,14 @@ int pci_iov_add_virtfn(struct pci_dev *dev, int id) virtfn->multifunction = 0; for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { - res = &dev->resource[i + PCI_IOV_RESOURCES]; + int idx = pci_resource_num_from_vf_bar(i); + + res = &dev->resource[idx]; if (!res->parent) continue; virtfn->resource[i].name = pci_name(virtfn); virtfn->resource[i].flags = res->flags; - size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); + size = pci_iov_resource_size(dev, idx); resource_set_range(&virtfn->resource[i], res->start + size * id, size); rc = request_resource(res, &virtfn->resource[i]); @@ -644,8 +646,10 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) nres = 0; for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { - bars |= (1 << (i + PCI_IOV_RESOURCES)); - res = &dev->resource[i + PCI_IOV_RESOURCES]; + int idx = pci_resource_num_from_vf_bar(i); + + bars |= (1 << idx); + res = &dev->resource[idx]; if (res->parent) nres++; } @@ -811,8 +815,10 @@ static int sriov_init(struct pci_dev *dev, int pos) nres = 0; for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { - res = &dev->resource[i + PCI_IOV_RESOURCES]; - res_name = pci_resource_name(dev, i + PCI_IOV_RESOURCES); + int idx = pci_resource_num_from_vf_bar(i); + + res = &dev->resource[idx]; + res_name = pci_resource_name(dev, idx); /* * If it is already FIXED, don't change it, something @@ -871,7 +877,7 @@ static int sriov_init(struct pci_dev *dev, int pos) dev->is_physfn = 0; failed: for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { - res = &dev->resource[i + PCI_IOV_RESOURCES]; + res = &dev->resource[pci_resource_num_from_vf_bar(i)]; res->flags = 0; } @@ -933,7 +939,7 @@ static void sriov_restore_state(struct pci_dev *dev) pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, ctrl); for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) - pci_update_resource(dev, i + PCI_IOV_RESOURCES); + pci_update_resource(dev, pci_resource_num_from_vf_bar(i)); pci_write_config_dword(dev, iov->pos + PCI_SRIOV_SYS_PGSIZE, iov->pgsz); pci_iov_set_numvfs(dev, iov->num_VFs); @@ -999,7 +1005,7 @@ void pci_iov_update_resource(struct pci_dev *dev, int resno) { struct pci_sriov *iov = dev->is_physfn ? dev->sriov : NULL; struct resource *res = pci_resource_n(dev, resno); - int vf_bar = resno - PCI_IOV_RESOURCES; + int vf_bar = pci_resource_num_to_vf_bar(resno); struct pci_bus_region region; u16 cmd; u32 new; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index adc54bb2c8b34..f44840ee3c327 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -693,6 +693,15 @@ static inline bool pci_resource_is_iov(int resno) { return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END; } +static inline int pci_resource_num_from_vf_bar(int resno) +{ + return resno + PCI_IOV_RESOURCES; +} + +static inline int pci_resource_num_to_vf_bar(int resno) +{ + return resno - PCI_IOV_RESOURCES; +} extern const struct attribute_group sriov_pf_dev_attr_group; extern const struct attribute_group sriov_vf_dev_attr_group; #else @@ -717,6 +726,16 @@ static inline bool pci_resource_is_iov(int resno) { return false; } +static inline int pci_resource_num_from_vf_bar(int resno) +{ + WARN_ON_ONCE(1); + return -ENODEV; +} +static inline int pci_resource_num_to_vf_bar(int resno) +{ + WARN_ON_ONCE(1); + return -ENODEV; +} #endif /* CONFIG_PCI_IOV */ #ifdef CONFIG_PCIE_TPH diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 54d6f4fa3ce16..281121449fc0b 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -1885,7 +1885,8 @@ static int iov_resources_unassigned(struct pci_dev *dev, void *data) bool *unassigned = data; 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The capability layout is the same as PCI_EXT_CAP_ID_REBAR, which means we can reuse most of the implementation, the only difference being resource size calculation (which is multiplied by total VFs) and memory decoding (which is controlled by a separate VF MSE field in SR-IOV cap). Extend the pci_resize_resource() function to accept IOV resources. See PCIe r6.2, sec 7.8.7. Signed-off-by: Michał Winiarski Reviewed-by: Ilpo Järvinen --- drivers/pci/iov.c | 21 +++++++++++++++++++++ drivers/pci/pci.c | 10 +++++++++- drivers/pci/pci.h | 9 +++++++++ drivers/pci/setup-res.c | 35 ++++++++++++++++++++++++++++++----- 4 files changed, 69 insertions(+), 6 deletions(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 3d5da055c3dc1..fee99e15a943f 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -154,6 +154,27 @@ resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) return dev->sriov->barsz[pci_resource_num_to_vf_bar(resno)]; } +void pci_iov_resource_set_size(struct pci_dev *dev, int resno, + resource_size_t size) +{ + if (!pci_resource_is_iov(resno)) { + pci_warn(dev, "%s is not an IOV resource\n", + pci_resource_name(dev, resno)); + return; + } + + dev->sriov->barsz[pci_resource_num_to_vf_bar(resno)] = size; +} + +bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) +{ + u16 cmd; + + pci_read_config_word(dev, dev->sriov->pos + PCI_SRIOV_CTRL, &cmd); + + return cmd & PCI_SRIOV_CTRL_MSE; +} + static void pci_read_vf_config_common(struct pci_dev *virtfn) { struct pci_dev *physfn = virtfn->physfn; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4d7c9f64ea24e..6878e3b1e3fcf 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -3745,7 +3745,15 @@ static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) unsigned int pos, nbars, i; u32 ctrl; - pos = pdev->rebar_cap; + if (pci_resource_is_iov(bar)) { + if (!pdev->physfn) + return -ENOTSUPP; + pos = pdev->sriov->vf_rebar_cap; + bar = pci_resource_num_to_vf_bar(bar); + } else { + pos = pdev->rebar_cap; + } + if (!pos) return -ENOTSUPP; diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index f44840ee3c327..643cd8c737f66 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -689,6 +689,9 @@ void pci_iov_update_resource(struct pci_dev *dev, int resno); resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); void pci_restore_iov_state(struct pci_dev *dev); int pci_iov_bus_range(struct pci_bus *bus); +void pci_iov_resource_set_size(struct pci_dev *dev, int resno, + resource_size_t size); +bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev); static inline bool pci_resource_is_iov(int resno) { return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END; @@ -722,6 +725,12 @@ static inline int pci_iov_bus_range(struct pci_bus *bus) { return 0; } +static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resno, + resource_size_t size) { } +static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) +{ + return false; +} static inline bool pci_resource_is_iov(int resno) { return false; diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index c6657cdd06f67..d2b3ed51e8804 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -423,13 +423,39 @@ void pci_release_resource(struct pci_dev *dev, int resno) } EXPORT_SYMBOL(pci_release_resource); +static bool pci_resize_is_memory_decoding_enabled(struct pci_dev *dev, + int resno) +{ + u16 cmd; + + if (pci_resource_is_iov(resno)) + return pci_iov_is_memory_decoding_enabled(dev); + + pci_read_config_word(dev, PCI_COMMAND, &cmd); + + return cmd & PCI_COMMAND_MEMORY; +} + +static void pci_resize_resource_set_size(struct pci_dev *dev, int resno, + int size) +{ + resource_size_t res_size = pci_rebar_size_to_bytes(size); + struct resource *res = pci_resource_n(dev, resno); + + if (!pci_resource_is_iov(resno)) { + resource_set_size(res, res_size); + } else { + resource_set_size(res, res_size * pci_sriov_get_totalvfs(dev)); + pci_iov_resource_set_size(dev, resno, res_size); + } +} + int pci_resize_resource(struct pci_dev *dev, int resno, int size) { struct resource *res = pci_resource_n(dev, resno); struct pci_host_bridge *host; int old, ret; u32 sizes; - u16 cmd; /* Check if we must preserve the firmware's resource assignment */ host = pci_find_host_bridge(dev->bus); @@ -440,8 +466,7 @@ int pci_resize_resource(struct pci_dev *dev, int resno, int size) if (!(res->flags & IORESOURCE_UNSET)) return -EBUSY; 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Wed, 2 Apr 2025 14:11:55 +0000 From: =?utf-8?q?Micha=C5=82_Winiarski?= To: , , , , "Bjorn Helgaas" , =?utf-8?q?Christian_K=C3=B6nig?= , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , =?utf-8?q?Ilpo_J=C3=A4rvi?= =?utf-8?q?nen?= CC: Rodrigo Vivi , Michal Wajdeczko , Lucas De Marchi , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Matt Roper , =?utf-8?q?Micha=C5=82_Winiarski?= Subject: [PATCH v7 4/6] PCI/IOV: Check that VF BAR fits within the reservation Date: Wed, 2 Apr 2025 16:11:20 +0200 Message-ID: <20250402141122.2818478-5-michal.winiarski@intel.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250402141122.2818478-1-michal.winiarski@intel.com> References: <20250402141122.2818478-1-michal.winiarski@intel.com> X-ClientProxiedBy: VI1PR09CA0127.eurprd09.prod.outlook.com (2603:10a6:803:12c::11) To DM4PR11MB5373.namprd11.prod.outlook.com (2603:10b6:5:394::7) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR11MB5373:EE_|SJ0PR11MB5213:EE_ X-MS-Office365-Filtering-Correlation-Id: 61fcf376-a4f5-41e2-7227-08dd71f052cf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|366016|376014; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?JGnWCPhlMNsXlnrCs7xByGu4qeeH?= =?utf-8?q?3/KIJLboyXhkFHqQhiwqnPwzZqhebIdOtCbiUu/OC4HsbUH+jHaQ5Q8RS29oQItkA?= =?utf-8?q?CUsao9WvN1i+GXAAohfRtU7Ul9c5VgdEhTQ0jisAKO72eg7cpI0Se0QbcD1zANr2H?= =?utf-8?q?+uKeqR73pOJ7vnyDYcY5c9WWHbH+PH4V8+qjcQyjhb5zqltQgQlKHKA9wj5fzkUGq?= =?utf-8?q?w5V3KHURR7BS474oDU3FFwOBp6ArSD1viPUN1SfFPE/1dElACSTeuskt1YsiydzjO?= =?utf-8?q?HBrs4+47rhsPJ1ehlje44F60dm3ZMH9E1gt4lWyA8BN+HuJKPQ3cLlICjby7GstmW?= =?utf-8?q?Fg2lx7wueo72e+i97YOMXiFrhEyYEwE8Xq/oZGjdKLMPtDx2ekBAFlWJtxJesnBld?= =?utf-8?q?FJZfZzxYwwsxP/JTxYb2RVi2CdfvO/cvaP55RR4pbS+kd6quHfpHsaDsBsqhN3NHY?= =?utf-8?q?ZCePx1c2xjTd95EW/iqt3Y8Vo9gGKecDUu11zljPJF+9RME4vfh2aNIat1kVWv1qQ?= =?utf-8?q?7QJUC7t5ddFY/ypIV4IYBHg9hnafoVERUYDoM/XJCwsHrG+hdkAjNIx1vVTDq/cEG?= =?utf-8?q?HfdJF298eUd+rpU/fF2OC4uIXM8mv6Obivc+hltdOHzRxXGBp3qeOLk4MZ0swXgI1?= =?utf-8?q?OKcoAqFKHPTY5yVfuTDihauVYbbOm85SGW4f12t6oh94cGq7IaZsWjfEo6XTGXrDs?= =?utf-8?q?C+EPWeEEviAtvawiJig8HjOKxSJEzp6Wka6nR1EBVi/s46r7PfD1Xn9UJwmrrkuxV?= =?utf-8?q?QS/rA/fydiuwQbM5nvIrHGg7tEZkoqaw4bpQd6a/Q53wybLz1wnKNO4as5RPsHGlG?= =?utf-8?q?FFbhBq0c+PL8otCNcn4XU3rtXT6SjqG/CIcXtyv1EbBr+X5zreibxFL1Zp7Ng70m7?= =?utf-8?q?/Wbs5VtxkLmnsdSqnaW1HBXSp9PhJSNMmjCytGf7cUjSCWQILBk/VL5I0TGyARwAU?= =?utf-8?q?oe+H5ggXwH60fmSIJ/0Qxz8Rrv2CzRWy5kyGF5ijmzO+5jdcfmnO8KpaBdgpaG5eG?= =?utf-8?q?aNzXoxpEXvnNw26GrJnQTfZ5qz+pTP2u7CMs8JEa/bzOZ8KvijMAG1y9O79VtytAu?= =?utf-8?q?d84QTgpTvTJv7rz7rKSFek0vObBzw6qI/lGDl/Qmc5LkhkfvkNHx226opLHmTutLy?= =?utf-8?q?a1kGA7Z+VYQvQhBlMqGCXWcj/p6uGhv0EIYcPpk6JmgoCZ7rwa7fHlhNBKi3TzI4T?= =?utf-8?q?MHUUvBdup6is5ptqjEEZXT9kS+YQLq0/F1L+PByj1XuIRkOhTYf7LBPP53xezYwu+?= =?utf-8?q?fzMfmCvZuVvLTg255yBL99kiXrrxoQzV32L5D1FzsEdNfER0lvgRLzUPRb8QhIX8C?= =?utf-8?q?aUe1s0fIW3Xjshu1pzC2mka//TXdK9Ps3ak1I6vbdYJp/8EqWepmqZ2aDsdxjWnGc?= =?utf-8?q?REoP4bB47lqa9xIUI1k8FXy4uAm++NCnGLTXFENLtDxoJbLl+vy8fucwTxEdosXpe?= =?utf-8?q?5Mt4lnebv68xkOiD8wai33zLFpJkLgdU/QXBK7DybrUSJCvJZsuiBoKiZR8dY2W46?= =?utf-8?q?fagAitkrnIph9Gu68Pt1/WuVhGlhfSUWjw=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 61fcf376-a4f5-41e2-7227-08dd71f052cf X-MS-Exchange-CrossTenant-AuthSource: DM4PR11MB5373.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2025 14:11:55.5364 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: C29O/bJfiTtbiR9YDfFR238o1GbVCTKtNnVY0J2VEc46MzeMTkt1kbu0XSDcKoQ+Ls78joeval7edU80QffA/VI2Jr6z0kREHX+28JzHV9k= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR11MB5213 X-OriginatorOrg: intel.com When the resource representing VF MMIO BAR reservation is created, its size is always large enough to accommodate the BAR of all SR-IOV Virtual Functions that can potentially be created (total VFs). If for whatever reason it's not possible to accommodate all VFs - the resource is not assigned and no VFs can be created. An upcoming change will allow VF BAR size to be modified by drivers at a later point in time, which means that the check for resource assignment is no longer sufficient. Add an additional check that verifies that VF BAR for all enabled VFs fits within the underlying reservation resource. Signed-off-by: Michał Winiarski Reviewed-by: Ilpo Järvinen --- drivers/pci/iov.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index fee99e15a943f..2fafbd6a998f0 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -668,9 +668,12 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) nres = 0; for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { int idx = pci_resource_num_from_vf_bar(i); + resource_size_t vf_bar_sz = pci_iov_resource_size(dev, idx); bars |= (1 << idx); res = &dev->resource[idx]; + if (vf_bar_sz * nr_virtfn > resource_size(res)) + continue; if (res->parent) nres++; } From patchwork Wed Apr 2 14:11:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Micha=C5=82_Winiarski?= X-Patchwork-Id: 14036086 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C27FA23C388; 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Wed, 2 Apr 2025 14:12:00 +0000 From: =?utf-8?q?Micha=C5=82_Winiarski?= To: , , , , "Bjorn Helgaas" , =?utf-8?q?Christian_K=C3=B6nig?= , =?utf-8?q?Krzy?= =?utf-8?q?sztof_Wilczy=C5=84ski?= , =?utf-8?q?Ilpo_J=C3=A4rvi?= =?utf-8?q?nen?= CC: Rodrigo Vivi , Michal Wajdeczko , Lucas De Marchi , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Matt Roper , =?utf-8?q?Micha=C5=82_Winiarski?= Subject: [PATCH v7 5/6] PCI: Allow drivers to control VF BAR size Date: Wed, 2 Apr 2025 16:11:21 +0200 Message-ID: <20250402141122.2818478-6-michal.winiarski@intel.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250402141122.2818478-1-michal.winiarski@intel.com> References: <20250402141122.2818478-1-michal.winiarski@intel.com> X-ClientProxiedBy: VE1PR03CA0037.eurprd03.prod.outlook.com (2603:10a6:803:118::26) To DM4PR11MB5373.namprd11.prod.outlook.com (2603:10b6:5:394::7) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR11MB5373:EE_|SJ0PR11MB5213:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f8268e3-4db7-4b21-7bb2-08dd71f055e3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|366016|376014; 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Add a pci_iov_vf_bar_set_size() function to control the size and a pci_iov_vf_bar_get_sizes() helper to get the VF BAR sizes that will allow up to num_vfs to be successfully enabled with the current underlying reservation size. Signed-off-by: Michał Winiarski --- drivers/pci/iov.c | 69 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 6 ++++ 2 files changed, 75 insertions(+) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 2fafbd6a998f0..8a62049b56b41 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -1313,3 +1313,72 @@ int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn) return nr_virtfn; } EXPORT_SYMBOL_GPL(pci_sriov_configure_simple); + +/** + * pci_iov_vf_bar_set_size - set a new size for a VF BAR + * @dev: the PCI device + * @resno: the resource number + * @size: new size as defined in the spec (0=1MB, 31=128TB) + * + * Set the new size of a VF BAR that supports VF resizable BAR capability. + * Unlike pci_resize_resource(), this does not cause the resource that + * reserves the MMIO space (originally up to total_VFs) to be resized, which + * means that following calls to pci_enable_sriov() can fail if the resources + * no longer fit. + * + * Return: 0 on success, or negative on failure. + */ +int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size) +{ + int ret; + u32 sizes; + + if (!pci_resource_is_iov(resno)) + return -EINVAL; + + if (pci_iov_is_memory_decoding_enabled(dev)) + return -EBUSY; + + sizes = pci_rebar_get_possible_sizes(dev, resno); + if (!sizes) + return -ENOTSUPP; + + if (!(sizes & BIT(size))) + return -EINVAL; + + ret = pci_rebar_set_size(dev, resno, size); + if (ret) + return ret; + + pci_iov_resource_set_size(dev, resno, pci_rebar_size_to_bytes(size)); + + return 0; +} +EXPORT_SYMBOL_GPL(pci_iov_vf_bar_set_size); + +/** + * pci_iov_vf_bar_get_sizes - get VF BAR sizes allowing to create up to num_vfs + * @dev: the PCI device + * @resno: the resource number + * @num_vfs: number of VFs + * + * Get the sizes of a VF resizable BAR that can accommodate @num_vfs within + * the currently assigned size of the resource @resno. + * + * Return: A bitmask of sizes in format defined in the spec (bit 0=1MB, + * bit 31=128TB). + */ +u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs) +{ + resource_size_t vf_len = pci_resource_len(dev, resno); + u32 sizes; + + if (!num_vfs) + return 0; + + do_div(vf_len, num_vfs); + sizes = (roundup_pow_of_two(vf_len + 1) - 1) >> ilog2(SZ_1M); + + return sizes & pci_rebar_get_possible_sizes(dev, resno); +} +EXPORT_SYMBOL_GPL(pci_iov_vf_bar_get_sizes); diff --git a/include/linux/pci.h b/include/linux/pci.h index 0e8e3fd77e967..c8708f3749757 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -2389,6 +2389,8 @@ int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); int pci_sriov_get_totalvfs(struct pci_dev *dev); int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn); resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); +int pci_iov_vf_bar_set_size(struct pci_dev *dev, int resno, int size); +u32 pci_iov_vf_bar_get_sizes(struct pci_dev *dev, int resno, int num_vfs); void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe); /* Arch may override these (weak) */ @@ -2441,6 +2443,10 @@ static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) #define pci_sriov_configure_simple NULL static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) { return 0; 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This means that we can achieve full LMEM BAR access without the need to attempt full VF LMEM BAR resize via pci_resize_resource(). Always try to set the largest possible BAR size that allows to fit the number of enabled VFs and inform the user in case the resize attempt is not successful. Signed-off-by: Michał Winiarski Reviewed-by: Ilpo Järvinen --- drivers/gpu/drm/xe/regs/xe_bars.h | 1 + drivers/gpu/drm/xe/xe_pci_sriov.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_bars.h b/drivers/gpu/drm/xe/regs/xe_bars.h index ce05b6ae832f1..880140d6ccdca 100644 --- a/drivers/gpu/drm/xe/regs/xe_bars.h +++ b/drivers/gpu/drm/xe/regs/xe_bars.h @@ -7,5 +7,6 @@ #define GTTMMADR_BAR 0 /* MMIO + GTT */ #define LMEM_BAR 2 /* VRAM */ +#define VF_LMEM_BAR 9 /* VF VRAM */ #endif diff --git a/drivers/gpu/drm/xe/xe_pci_sriov.c b/drivers/gpu/drm/xe/xe_pci_sriov.c index 09ee8a06fe2ed..4be566331ee15 100644 --- a/drivers/gpu/drm/xe/xe_pci_sriov.c +++ b/drivers/gpu/drm/xe/xe_pci_sriov.c @@ -3,6 +3,10 @@ * Copyright © 2023-2024 Intel Corporation */ +#include +#include + +#include "regs/xe_bars.h" #include "xe_assert.h" #include "xe_device.h" #include "xe_gt_sriov_pf_config.h" @@ -111,6 +115,18 @@ static void pf_link_vfs(struct xe_device *xe, int num_vfs) } } +static int resize_vf_vram_bar(struct xe_device *xe, int num_vfs) +{ + struct pci_dev *pdev = to_pci_dev(xe->drm.dev); + u32 sizes; + + sizes = pci_iov_vf_bar_get_sizes(pdev, VF_LMEM_BAR, num_vfs); + if (!sizes) + return 0; + + return pci_iov_vf_bar_set_size(pdev, VF_LMEM_BAR, __fls(sizes)); +} + static int pf_enable_vfs(struct xe_device *xe, int num_vfs) { struct pci_dev *pdev = to_pci_dev(xe->drm.dev); @@ -137,6 +153,12 @@ static int pf_enable_vfs(struct xe_device *xe, int num_vfs) if (err < 0) goto failed; + if (IS_DGFX(xe)) { + err = resize_vf_vram_bar(xe, num_vfs); + if (err) + xe_sriov_info(xe, "Failed to set VF LMEM BAR size: %d\n", err); + } + err = pci_enable_sriov(pdev, num_vfs); if (err < 0) goto failed;