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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v4 1/3] xen/arm: Move some of the functions to common file Date: Thu, 3 Apr 2025 18:12:39 +0100 Message-ID: <20250403171241.975377-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250403171241.975377-1-ayan.kumar.halder@amd.com> References: <20250403171241.975377-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD6:EE_|IA1PR12MB6356:EE_ X-MS-Office365-Filtering-Correlation-Id: bbc10902-0735-4d6b-f89f-08dd72d2c811 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: MzbSPx4qmyJBklvTR8GMBHK+kCEYa7SHo1gQKBogzY9wMZbbIdJH8gnhdM6ttZYRj0SdP0qwt1u0gTf0rpgVcsKspF56/8XwSNbRwJPoMBp+5eOqMZrtTxgyBIGQQMJXTnErM+WMdtOrqWnbd7JP5knp123Gk1/ISRqJBhrmlAMqcI/hJnhF1f+i6wmYBBM94MzjBnlJUVJRPKA++q/4ATKqS8woU0d0/ecgjKV/iFKZmPkNq8+sW/8P5ywi+HLqHVowvNOHUdmZcZ9dIWms70VigqiDxfCaadD+QS5aEw3s2JFBqCo0exjWrWnPHc91J8AaG6G3GjK+AM4aMeJGJuauKESlMkXCzkYq+kF5iHpfMK+3TT0hD63QyBUcnwfxx6ycBKdQZjNvqHdTOiNgjXEWwLF2TVYJMqcdyUt52ZovD0wr7cSThH1kijEbkYX0LC5CcC7ADxPeAtO/MLWbrWTWwDM8n8rBURPhtxq2BTUR72vuFdQEGlkpKmRfBymrMC0Kc5nLaC2ZbowPojWxhIOiEszR74JCjsp+qGZDUFNXol6PefcyAr1C94DfsDM0tRmgSJklos5xGKheUqyWrF2JcTHeCHA7TQusHJJ9kNlcKnsMyygCmUVBFeDmbzDjd5hzGIPAW6gKsYGzkGkdTnPqnlSu+nhwyx8cKNMNM3P397tyIDBSM9LJy9wmPsbZFa0BdxwY+MWhNTMSXa7AdPD48/DGIaqbI0zwQ9doNA+mh56jLcOjO3ndzzYYCTfEiwRVT2t/LbqAeVujlTzNIzTA6y7wnO2D0L0c1SNznzYtoorV8A8WUYlRaY88XpPgdg4dvQw8iSgs3fhagNtU/N0vHRBMlJj8nBsO7/8DgA92nU3J4YEj9o4lsdaqrHGOIBWp+BXUN6pVpGFEfcXyl0I0mwFucWwu8GWQY7wXXa6Ue8fvQW/8pS2MgI6B7ctnUxGSQpyjy1YpXQ88KtVbCKgeQgrHM2F2U/9kgQky/5c2+UDqIN/M3GgwciuwiT2NgwFqHnx/dGYpeCm7FlVzp2dSg0+oAwTkZ64nW4ByhoyTfF+5glm9kUW9hDVCSutlz1RuLwaSxUFJV3Nd6Qh05YEhsoiy8/3tQhVguR+rQaEh2p+f8NGdFeaCHyGe2ea3OQmoCWS/CuuUD3fn5bFDa5XmusSMamA8Ol3Tksh9uNwNEfKzk8/bfilBlC57T9sO9hqmxM+4t2mofxFTAbWG6V3mzii+7OEddToOopkHaLZABDH2zCPd4mAWOCkp/qGMMCpz3O+c8tx5i9DQsx+E9XOcFzjCVWccPg4xm9ihzCY8alAQPDLfJ9n+Oh9U1XOmCKwOAnq5bcLTcy6DrqzXmHH04LdBsdeJcqEdqnJATAn846f4XEXsnlRWNLjmB75hazoM5xw2QT2VcswTahdlnrRj40SM1/rh2AWnrY2VVKDbsNHiMc1FMjMW34BlS62oN8hqd0M0DAQGm5thPpD2Qln2fx5o/Fut2ax0fY43sog= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2025 17:12:58.0235 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bbc10902-0735-4d6b-f89f-08dd72d2c811 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD6.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6356 Added a new file prepare_xen_region.inc to hold the common earlyboot MPU regions configurations across arm64 and arm32. prepare_xen_region, fail_insufficient_regions() will be used by both arm32 and arm64. Thus, they have been moved to prepare_xen_region.inc. enable_secondary_cpu_mm() is a stub which is moved to prepare_xen_region.inc as SMP is currently not supported for MPU. *_PRBAR are moved to arm64/sysregs.h. *_PRLAR are moved to prepare_xen_region.inc as they are common between arm32 and arm64. Introduce WRITE_SYSREG_ASM to write to the system registers from the common asm file. Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Extracted the arm64 head.S functions/macros in a common file. v3 - 1. Moved *_PRLAR are moved to prepare_xen_region.inc 2. enable_boot_cpu_mm() is preserved in mpu/head.S. 3. STORE_SYSREG is renamed as WRITE_SYSREG_ASM() 4. LOAD_SYSREG is removed. 5. No need to save/restore lr in enable_boot_cpu_mm(). IOW, keep it as it was in the original code. xen/arch/arm/arm64/mpu/head.S | 88 +----------------- xen/arch/arm/include/asm/arm64/sysregs.h | 11 +++ .../include/asm/mpu/prepare_xen_region.inc | 89 +++++++++++++++++++ 3 files changed, 101 insertions(+), 87 deletions(-) create mode 100644 xen/arch/arm/include/asm/mpu/prepare_xen_region.inc diff --git a/xen/arch/arm/arm64/mpu/head.S b/xen/arch/arm/arm64/mpu/head.S index ed01993d85..8cd8107a13 100644 --- a/xen/arch/arm/arm64/mpu/head.S +++ b/xen/arch/arm/arm64/mpu/head.S @@ -3,83 +3,7 @@ * Start-of-day code for an Armv8-R MPU system. */ -#include -#include - -/* Backgroud region enable/disable */ -#define SCTLR_ELx_BR BIT(17, UL) - -#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ -#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ -#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ -#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */ - -#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ -#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ - -/* - * Macro to prepare and set a EL2 MPU memory region. - * We will also create an according MPU memory region entry, which - * is a structure of pr_t, in table \prmap. - * - * sel: region selector - * base: reg storing base address - * limit: reg storing limit address - * prbar: store computed PRBAR_EL2 value - * prlar: store computed PRLAR_EL2 value - * maxcount: maximum number of EL2 regions supported - * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be - * REGION_DATA_PRBAR - * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be - * REGION_NORMAL_PRLAR - * - * Preserves \maxcount - * Output: - * \sel: Next available region selector index. - * Clobbers \base, \limit, \prbar, \prlar - * - * Note that all parameters using registers should be distinct. - */ -.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR - /* Check if the region is empty */ - cmp \base, \limit - beq 1f - - /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ - cmp \sel, \maxcount - bge fail_insufficient_regions - - /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ - and \base, \base, #MPU_REGION_MASK - mov \prbar, #\attr_prbar - orr \prbar, \prbar, \base - - /* Limit address should be inclusive */ - sub \limit, \limit, #1 - and \limit, \limit, #MPU_REGION_MASK - mov \prlar, #\attr_prlar - orr \prlar, \prlar, \limit - - msr PRSELR_EL2, \sel - isb - msr PRBAR_EL2, \prbar - msr PRLAR_EL2, \prlar - dsb sy - isb - - add \sel, \sel, #1 - -1: -.endm - -/* - * Failure caused due to insufficient MPU regions. - */ -FUNC_LOCAL(fail_insufficient_regions) - PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") -1: wfe - b 1b -END(fail_insufficient_regions) +#include /* * Enable EL2 MPU and data cache @@ -154,16 +78,6 @@ FUNC(enable_boot_cpu_mm) ret END(enable_boot_cpu_mm) -/* - * We don't yet support secondary CPUs bring-up. Implement a dummy helper to - * please the common code. - */ -FUNC(enable_secondary_cpu_mm) - PRINT("- SMP not enabled yet -\r\n") -1: wfe - b 1b -END(enable_secondary_cpu_mm) - /* * Local variables: * mode: ASM diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h index b593e4028b..3ee3715430 100644 --- a/xen/arch/arm/include/asm/arm64/sysregs.h +++ b/xen/arch/arm/include/asm/arm64/sysregs.h @@ -462,6 +462,15 @@ #define ZCR_ELx_LEN_SIZE 9 #define ZCR_ELx_LEN_MASK 0x1ff +#define REGION_TEXT_PRBAR 0x38 /* SH=11 AP=10 XN=00 */ +#define REGION_RO_PRBAR 0x3A /* SH=11 AP=10 XN=10 */ +#define REGION_DATA_PRBAR 0x32 /* SH=11 AP=00 XN=10 */ +#define REGION_DEVICE_PRBAR 0x22 /* SH=10 AP=00 XN=10 */ + +#define WRITE_SYSREG_ASM(v, name) "msr " __stringify(name,) #v; + +#ifndef __ASSEMBLY__ + /* Access to system registers */ #define WRITE_SYSREG64(v, name) do { \ @@ -481,6 +490,8 @@ #define WRITE_SYSREG_LR(v, index) WRITE_SYSREG(v, ICH_LR_REG(index)) #define READ_SYSREG_LR(index) READ_SYSREG(ICH_LR_REG(index)) +#endif /* __ASSEMBLY__ */ + #endif /* _ASM_ARM_ARM64_SYSREGS_H */ /* diff --git a/xen/arch/arm/include/asm/mpu/prepare_xen_region.inc b/xen/arch/arm/include/asm/mpu/prepare_xen_region.inc new file mode 100644 index 0000000000..8af44d5669 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/prepare_xen_region.inc @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Backgroud region enable/disable */ +#define SCTLR_ELx_BR BIT(17, UL) + +#define REGION_NORMAL_PRLAR 0x0f /* NS=0 ATTR=111 EN=1 */ +#define REGION_DEVICE_PRLAR 0x09 /* NS=0 ATTR=100 EN=1 */ + +/* + * Macro to prepare and set a EL2 MPU memory region. + * We will also create an according MPU memory region entry, which + * is a structure of pr_t, in table \prmap. + * + * sel: region selector + * base: reg storing base address + * limit: reg storing limit address + * prbar: store computed PRBAR_EL2 value + * prlar: store computed PRLAR_EL2 value + * maxcount: maximum number of EL2 regions supported + * attr_prbar: PRBAR_EL2-related memory attributes. If not specified it will be + * REGION_DATA_PRBAR + * attr_prlar: PRLAR_EL2-related memory attributes. If not specified it will be + * REGION_NORMAL_PRLAR + * + * Preserves maxcount + * Output: + * sel: Next available region selector index. + * Clobbers base, limit, prbar, prlar + * + * Note that all parameters using registers should be distinct. + */ +.macro prepare_xen_region, sel, base, limit, prbar, prlar, maxcount, attr_prbar=REGION_DATA_PRBAR, attr_prlar=REGION_NORMAL_PRLAR + /* Check if the region is empty */ + cmp \base, \limit + beq 1f + + /* Check if the number of regions exceeded the count specified in MPUIR_EL2 */ + cmp \sel, \maxcount + bge fail_insufficient_regions + + /* Prepare value for PRBAR_EL2 reg and preserve it in \prbar.*/ + and \base, \base, #MPU_REGION_MASK + mov \prbar, #\attr_prbar + orr \prbar, \prbar, \base + + /* Limit address should be inclusive */ + sub \limit, \limit, #1 + and \limit, \limit, #MPU_REGION_MASK + mov \prlar, #\attr_prlar + orr \prlar, \prlar, \limit + + WRITE_SYSREG_ASM(\sel, PRSELR_EL2) + isb + WRITE_SYSREG_ASM(\prbar, PRBAR_EL2) + WRITE_SYSREG_ASM(\prlar, PRLAR_EL2) + dsb sy + isb + + add \sel, \sel, #1 + +1: +.endm + +/* Failure caused due to insufficient MPU regions. */ +FUNC_LOCAL(fail_insufficient_regions) + PRINT("- Selected MPU region is above the implemented number in MPUIR_EL2 -\r\n") +1: wfe + b 1b +END(fail_insufficient_regions) + +/* + * We don't yet support secondary CPUs bring-up. Implement a dummy helper to + * please the common code. + */ +FUNC(enable_secondary_cpu_mm) + PRINT("- SMP not enabled yet -\r\n") +1: wfe + b 1b +END(enable_secondary_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ From patchwork Thu Apr 3 17:12:40 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 14036779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53A98C3601A for ; Thu, 3 Apr 2025 17:13:23 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.936975.1338076 (Exim 4.92) (envelope-from ) id 1u0O7n-00068m-P1; Thu, 03 Apr 2025 17:13:07 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 936975.1338076; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2025 17:12:59.4107 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 26cfe95f-cc09-42c2-3fc9-08dd72d2c8e3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9003 We have created the same boot-time MPU protection regions as Armv8-R AArch64. Also, we have defined *_PRBAR macros for arm32. The only difference from arm64 is that XN is 1-bit for arm32. The macros have been defined in mpu/cpregs.h. Also defined WRITE_SYSREG_ASM() to write to system registers in assembly. Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. enable_mpu() now sets HMAIR{0,1} registers. This is similar to what is being done in enable_mmu(). All the mm related configurations happen in this function. 2. Fixed some typos. v2 - 1. Include the common prepare_xen_region.inc in head.S. 2. Define LOAD_SYSREG()/STORE_SYSREG() for arm32. v3 - 1. Rename STORE_SYSREG() as WRITE_SYSREG_ASM() 2. enable_boot_cpu_mm() is defined in head.S xen/arch/arm/arm32/Makefile | 1 + xen/arch/arm/arm32/mpu/Makefile | 1 + xen/arch/arm/arm32/mpu/head.S | 91 +++++++++++++++++++++++++++ xen/arch/arm/include/asm/cpregs.h | 4 ++ xen/arch/arm/include/asm/mpu/cpregs.h | 30 +++++++++ 5 files changed, 127 insertions(+) create mode 100644 xen/arch/arm/arm32/mpu/Makefile create mode 100644 xen/arch/arm/arm32/mpu/head.S create mode 100644 xen/arch/arm/include/asm/mpu/cpregs.h diff --git a/xen/arch/arm/arm32/Makefile b/xen/arch/arm/arm32/Makefile index 40a2b4803f..537969d753 100644 --- a/xen/arch/arm/arm32/Makefile +++ b/xen/arch/arm/arm32/Makefile @@ -1,5 +1,6 @@ obj-y += lib/ obj-$(CONFIG_MMU) += mmu/ +obj-$(CONFIG_MPU) += mpu/ obj-$(CONFIG_EARLY_PRINTK) += debug.o obj-y += domctl.o diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makefile new file mode 100644 index 0000000000..3340058c08 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -0,0 +1 @@ +obj-y += head.o diff --git a/xen/arch/arm/arm32/mpu/head.S b/xen/arch/arm/arm32/mpu/head.S new file mode 100644 index 0000000000..719ae3624e --- /dev/null +++ b/xen/arch/arm/arm32/mpu/head.S @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Start-of-day code for an Armv8-R MPU system. + */ + +#include +#include +#include + +/* + * Set up the memory attribute type tables and enable EL2 MPU and data cache. + * If the Background region is enabled, then the MPU uses the default memory + * map as the Background region for generating the memory + * attributes when MPU is disabled. + * Since the default memory map of the Armv8-R AArch32 architecture is + * IMPLEMENTATION DEFINED, we intend to turn off the Background region here. + * + * Clobbers r0 - r1 + */ +FUNC_LOCAL(enable_mpu) + /* Set up memory attribute type tables */ + mov_w r0, MAIR0VAL + mov_w r1, MAIR1VAL + mcr CP32(r0, HMAIR0) + mcr CP32(r1, HMAIR1) + + mrc CP32(r0, HSCTLR) + bic r0, r0, #SCTLR_ELx_BR /* Disable Background region */ + orr r0, r0, #SCTLR_Axx_ELx_M /* Enable MPU */ + orr r0, r0, #SCTLR_Axx_ELx_C /* Enable D-cache */ + mcr CP32(r0, HSCTLR) + isb + + ret +END(enable_mpu) + +/* + * Maps the various sections of Xen (described in xen.lds.S) as different MPU + * regions. + * + * Clobbers r0 - r5 + * + */ +FUNC(enable_boot_cpu_mm) + /* Get the number of regions specified in MPUIR_EL2 */ + mrc CP32(r5, MPUIR_EL2) + and r5, r5, #NUM_MPU_REGIONS_MASK + + /* x0: region sel */ + mov r0, #0 + /* Xen text section. */ + mov_w r1, _stext + mov_w r2, _etext + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_TEXT_PRBAR + + /* Xen read-only data section. */ + mov_w r1, _srodata + mov_w r2, _erodata + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_RO_PRBAR + + /* Xen read-only after init and data section. (RW data) */ + mov_w r1, __ro_after_init_start + mov_w r2, __init_begin + prepare_xen_region r0, r1, r2, r3, r4, r5 + + /* Xen code section. */ + mov_w r1, __init_begin + mov_w r2, __init_data_begin + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_TEXT_PRBAR + + /* Xen data and BSS section. */ + mov_w r1, __init_data_begin + mov_w r2, __bss_end + prepare_xen_region r0, r1, r2, r3, r4, r5 + +#ifdef CONFIG_EARLY_PRINTK + /* Xen early UART section. */ + mov_w r1, CONFIG_EARLY_UART_BASE_ADDRESS + mov_w r2, (CONFIG_EARLY_UART_BASE_ADDRESS + CONFIG_EARLY_UART_SIZE) + prepare_xen_region r0, r1, r2, r3, r4, r5, attr_prbar=REGION_DEVICE_PRBAR, attr_prlar=REGION_DEVICE_PRLAR +#endif + + b enable_mpu +END(enable_boot_cpu_mm) + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h index aec9e8f329..6019a2cbdd 100644 --- a/xen/arch/arm/include/asm/cpregs.h +++ b/xen/arch/arm/include/asm/cpregs.h @@ -1,6 +1,10 @@ #ifndef __ASM_ARM_CPREGS_H #define __ASM_ARM_CPREGS_H +#ifdef CONFIG_MPU +#include +#endif + /* * AArch32 Co-processor registers. * diff --git a/xen/arch/arm/include/asm/mpu/cpregs.h b/xen/arch/arm/include/asm/mpu/cpregs.h new file mode 100644 index 0000000000..66871379a5 --- /dev/null +++ b/xen/arch/arm/include/asm/mpu/cpregs.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_ARM_MPU_CPREGS_H +#define __ASM_ARM_MPU_CPREGS_H + +#define REGION_TEXT_PRBAR 0x18 /* SH=11 AP=10 XN=0 */ +#define REGION_RO_PRBAR 0x1D /* SH=11 AP=10 XN=1 */ +#define REGION_DATA_PRBAR 0x19 /* SH=11 AP=00 XN=1 */ +#define REGION_DEVICE_PRBAR 0x11 /* SH=10 AP=00 XN=1 */ + +#define HMPUIR p15,4,c0,c0,4 + +/* CP15 CR6: MPU Protection Region Base/Limit/Select Address Register */ +#define HPRSELR p15,4,c6,c2,1 +#define PRBAR_EL2 p15,4,c6,c3,0 +#define PRLAR_EL2 p15,4,c6,c8,1 + +#define MPUIR_EL2 HMPUIR +#define PRSELR_EL2 HPRSELR + +#define WRITE_SYSREG_ASM(v, name) mcr CP32(v, name) + +#endif /* __ASM_ARM_MPU_CPREGS_H */ + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ From patchwork Thu Apr 3 17:12:41 2025 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: Ayan Kumar Halder , Stefano Stabellini , Julien Grall , Bertrand Marquis , Michal Orzel , "Volodymyr Babchuk" Subject: [PATCH v4 3/3] xen/arm32: mpu: Stubs to build MPU for arm32 Date: Thu, 3 Apr 2025 18:12:41 +0100 Message-ID: <20250403171241.975377-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250403171241.975377-1-ayan.kumar.halder@amd.com> References: <20250403171241.975377-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: ayan.kumar.halder@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F0:EE_|CYXPR12MB9425:EE_ X-MS-Office365-Filtering-Correlation-Id: 862b974f-9f7a-4d42-5303-08dd72d2ca9c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: uloNzALX8F/VGB8+8su6jVSsMKSlKErxVqlYBO2tzXTza5ov1yNHDcsm0ZojDLnM7WDFwyK28ti/bI09solcczbjka/S7eWXPfU04ddqHsRdt44lQcY3y7fKtKqsKW7/5nVSt36tnUq8/ObKEQYRRqqAkzoCJNCFZGe6QXkZWs0govF4trhZeMUAthTgkxUSycwkJHnzYvdnHQiwkZ2BbntNCMdCqtfLERbeOzSGhhYE14DOyyd7FGy9i4cPQcq6b47NmSIh3hzROEUao6ESoVFrxHLxXqBBE6HuIwz7OAXxwdUJXcpjeEv/F+oThp4wKyw2Zja2IdgQ0ujwVgx7h6kYWIQrwdE3apfk/qv63qoXFwwgsebou9YrLTdMlkCny4BlJpMBKRGtVFefOfY+26IE/+kr4c9ZVWp+tdTAA5pDikqw40Y4BsGg+iamPGnvrMWOtqRaTar/xVsymxNFnFu5t1FqyfS330xfT+EljJOIHFv4YkVZmTWeejKoTHspZCIMRrCBD+pvS3PtzZCOi+eF5UC3Y/q5b3c2N0xehqctsPywZFfdHBoA2p4n9CuaQyz8bjRcqfq8c9ryWBrgv/yFltv+V6RQ40E9DgVytHi0t4tWmJUUdWs9ImZ2JD7majtMuYzli+EnmK27NB5n4YR02wriYuHj4b5hGmfUycRm98VFXhEJRwdU0IWpgK4d/ngcvygjm2/7zogAH5zh2sKINRm9QV54GYF+3hvw0JAsi+mcfDsD+1iDAl89nse0LZTq6F3y8EfohUM+jsVeeROjhLEVeUoarsOC6k+qpTWZjkjaygJSlLyP9bNIeiadjjxMCBjlkyZ1ejHDM1Ibf9Lb5LDL23cm2i9NQPs+aN512sY4cfgAkwtorzzchQ96b2xnhQep8oHsJZH2B3oAmvhsC8B76JwxaLJlu07419bQ61lFd2DAiVd8JnKNcuPP68OEDfGuPRiGqn5qzypVg5TbF4KnQk7ZPPQUCQuMa26KhryN4VN7SszAEyRSEyhEJFj6nDTC4JwOK3fZCoBB4UaaDcJ1olUaVAzoQHm8+YxlNvxaBbD3sWAFCPVFKYkn3x80hdSCJm7bewbG5Q8/4SlDxr5bMsYrOZVOfDmhCZFkWPKdPWtwByRKPtFmSPdF1eghBztDYfBkcf/V3nVxWztXq7TPbjGcuyZCEPuSl7J3auW5GGB/MWdSDsaxLtl8ckyauBvJkR30AcC4vvulnLl0cZy4NT1cmDMGD0o9fSkzQnDZ7UfpEOprgulzT0cUNs/ikcE8HTuhMe3CZiVBSN9QV5ZhcDXdSqZBywFX4KSB2YyqeQ9MwMMUUt2mU5hN6lIqlTSdMfgUg5YUEqkx7zoceYI1wvIxEkmRf2c6BzJAUf/MqnOn9tcAypD9bUD9feBRpDA3CKsYQnAEa0i13nqvUFl1ngx6EYDYeC79SOj13Y52gM2qLydqDjQL5LussWlyFRF2ysewcqtsnDbyp/ggVKUhNSQskDvS+RwY5Zk= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2025 17:13:02.3013 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 862b974f-9f7a-4d42-5303-08dd72d2ca9c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9425 Add stubs to enable compilation Signed-off-by: Ayan Kumar Halder --- Changes from :- v1, v2 - 1. New patch introduced in v3. 2. Should be applied on top of https://patchwork.kernel.org/project/xen-devel/cover/20250316192445.2376484-1-luca.fancellu@arm.com/ v3 - 1. Add stubs for map_domain_page() and similar functions. 2. 'BUG_ON("unimplemented")' is kept in all the stubs. xen/arch/arm/arm32/mpu/Makefile | 2 ++ xen/arch/arm/arm32/mpu/p2m.c | 18 ++++++++++++++ xen/arch/arm/arm32/mpu/smpboot.c | 23 ++++++++++++++++++ xen/arch/arm/include/asm/mm.h | 5 ++++ xen/arch/arm/mpu/Makefile | 1 + xen/arch/arm/mpu/domain_page.c | 40 ++++++++++++++++++++++++++++++++ 6 files changed, 89 insertions(+) create mode 100644 xen/arch/arm/arm32/mpu/p2m.c create mode 100644 xen/arch/arm/arm32/mpu/smpboot.c create mode 100644 xen/arch/arm/mpu/domain_page.c diff --git a/xen/arch/arm/arm32/mpu/Makefile b/xen/arch/arm/arm32/mpu/Makefile index 3340058c08..38797f28af 100644 --- a/xen/arch/arm/arm32/mpu/Makefile +++ b/xen/arch/arm/arm32/mpu/Makefile @@ -1 +1,3 @@ obj-y += head.o +obj-y += smpboot.o +obj-y += p2m.o diff --git a/xen/arch/arm/arm32/mpu/p2m.c b/xen/arch/arm/arm32/mpu/p2m.c new file mode 100644 index 0000000000..df8de5c7d8 --- /dev/null +++ b/xen/arch/arm/arm32/mpu/p2m.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void __init setup_virt_paging(void) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/arm32/mpu/smpboot.c b/xen/arch/arm/arm32/mpu/smpboot.c new file mode 100644 index 0000000000..3f3e54294e --- /dev/null +++ b/xen/arch/arm/arm32/mpu/smpboot.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +int prepare_secondary_mm(int cpu) +{ + BUG_ON("unimplemented"); + return -EINVAL; +} + +void update_boot_mapping(bool enable) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/include/asm/mm.h b/xen/arch/arm/include/asm/mm.h index fbffaccef4..2a52cf530f 100644 --- a/xen/arch/arm/include/asm/mm.h +++ b/xen/arch/arm/include/asm/mm.h @@ -171,12 +171,17 @@ struct page_info #define PGC_need_scrub PGC_allocated #ifdef CONFIG_ARM_32 +#ifdef CONFIG_MPU +#define is_xen_heap_page(page) ({ BUG_ON("unimplemented"); false; }) +#define is_xen_heap_mfn(mfn) ({ BUG_ON("unimplemented"); false; }) +#else /* !CONFIG_MPU */ #define is_xen_heap_page(page) is_xen_heap_mfn(page_to_mfn(page)) #define is_xen_heap_mfn(mfn) ({ \ unsigned long mfn_ = mfn_x(mfn); \ (mfn_ >= mfn_x(directmap_mfn_start) && \ mfn_ < mfn_x(directmap_mfn_end)); \ }) +#endif /* !CONFIG_MPU */ #else #define is_xen_heap_page(page) ((page)->count_info & PGC_xen_heap) #define is_xen_heap_mfn(mfn) \ diff --git a/xen/arch/arm/mpu/Makefile b/xen/arch/arm/mpu/Makefile index 21bbc517b5..ff221011d5 100644 --- a/xen/arch/arm/mpu/Makefile +++ b/xen/arch/arm/mpu/Makefile @@ -2,3 +2,4 @@ obj-y += mm.o obj-y += p2m.o obj-y += setup.init.o obj-y += vmap.o +obj-$(CONFIG_ARM_32) += domain_page.o diff --git a/xen/arch/arm/mpu/domain_page.c b/xen/arch/arm/mpu/domain_page.c new file mode 100644 index 0000000000..b9ebb03d67 --- /dev/null +++ b/xen/arch/arm/mpu/domain_page.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include + +void *map_domain_page_global(mfn_t mfn) +{ + BUG_ON("unimplemented"); + return (void*)0; +} + +/* Map a page of domheap memory */ +void *map_domain_page(mfn_t mfn) +{ + BUG_ON("unimplemented"); + return (void*)0; +} + +/* Release a mapping taken with map_domain_page() */ +void unmap_domain_page(const void *ptr) +{ + BUG_ON("unimplemented"); +} + +mfn_t domain_page_map_to_mfn(const void *ptr) +{ + BUG_ON("unimplemented"); +} + +void unmap_domain_page_global(const void *va) +{ + BUG_ON("unimplemented"); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */