From patchwork Fri Apr 4 09:49:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teddy Astie X-Patchwork-Id: 14038263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7188C3601E for ; Fri, 4 Apr 2025 09:49:56 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.938000.1338838 (Exim 4.92) (envelope-from ) id 1u0dgF-00053Q-Lt; Fri, 04 Apr 2025 09:49:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 938000.1338838; Fri, 04 Apr 2025 09:49:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u0dgF-00053J-JN; Fri, 04 Apr 2025 09:49:43 +0000 Received: by outflank-mailman (input) for mailman id 938000; Fri, 04 Apr 2025 09:49:42 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u0dgE-0004pH-1U for xen-devel@lists.xenproject.org; Fri, 04 Apr 2025 09:49:42 +0000 Received: from mail186-2.suw21.mandrillapp.com (mail186-2.suw21.mandrillapp.com [198.2.186.2]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 1de0ab3a-113a-11f0-9eaa-5ba50f476ded; Fri, 04 Apr 2025 11:49:36 +0200 (CEST) Received: from pmta10.mandrill.prod.suw01.rsglab.com (localhost [127.0.0.1]) by mail186-2.suw21.mandrillapp.com (Mailchimp) with ESMTP id 4ZTYjW1nSvzS62PwT for ; Fri, 4 Apr 2025 09:49:35 +0000 (GMT) Received: from [37.26.189.201] by mandrillapp.com id c3e6aab71ed94423bea11c3c0a6a19ba; Fri, 04 Apr 2025 09:49:35 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 1de0ab3a-113a-11f0-9eaa-5ba50f476ded DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mandrillapp.com; s=mte1; t=1743760175; x=1744030175; bh=L6j027iimQgxGcnmldIIXGn1WhbaXyI2jdeQ52zotUM=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=Ke4Q9YBpahNvj6SX0beD4t4f6eTW79lJByjoNk/qYYCcJRENMiyMVMMCm6j5sMWVp CHlkdSFfhbxAqJ+O1p6uSSl8x204nOaoKhQmPLEskLsFOKYHosBfIaa1w8FQ4o7TEp 3XLp0sjMEMaON3Os034DJZFyw+cABLE8r26rWzwQoAxc6OXd2SJcCwqIT4TtB6zaSP MnyO1+OHEjazvjVLp32maXXRntZ0njO6nXd0SWSiOE0/DxPEcVdcfW/fIJzSoGxjaa VOkFJlXoiairinZQvOHCKWTtsNBhWtp1n48xcSPv2FZDFwGcKIV/dSo/SaiKgjn5m1 8WSFkSsBvSD/g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vates.tech; s=mte1; t=1743760175; x=1744020675; i=teddy.astie@vates.tech; bh=L6j027iimQgxGcnmldIIXGn1WhbaXyI2jdeQ52zotUM=; h=From:Subject:To:Cc:Message-Id:In-Reply-To:References:Feedback-ID: Date:MIME-Version:Content-Type:Content-Transfer-Encoding:CC:Date: Subject:From; b=M9TEAbZx34JpPJfz1gHk2GzHZmQxKFd2+n3ZWaOQ7bl7RzIteCwtz0o8fHBzOHo1L HIb/xk0C7UUC8MrwBkU9vlz4GKdcJsdWSxvvtn+MCtGRXcPd0KKKfQf+/4mtD6nHvy IWdfYZPBieChbYNu0uJivHvx/phLycPViSzatuJCDcG98Tx6bB1+A41WJLm5fOnyNB RmXDN9d+PzQ+KrqrUvNGNtAkJYF7usgR13iAJnDK4KDexWlPq1OsmdtVTrySJEmzU8 rxeQ+yzCFFXXpCl/ItxgZ5Cncv8awSTnwhLd01V2LD5wNaEaZP7fTSYqOvrwTtH0Jb Nf29GRb+rSelg== From: "Teddy Astie" Subject: =?utf-8?q?=5BPATCH_v2_1/2=5D_x86/amd=3A_Add_guest_support_for_AMD_T?= =?utf-8?q?CE?= X-Mailer: git-send-email 2.47.2 X-Bm-Disclaimer: Yes X-Bm-Milter-Handled: 4ffbd6c1-ee69-4e1b-aabd-f977039bd3e2 X-Bm-Transport-Timestamp: 1743760173257 To: xen-devel@lists.xenproject.org Cc: "Teddy Astie" , "Oleksii Kurochko" , "Community Manager" , "Jan Beulich" , "Andrew Cooper" , " =?utf-8?q?Roger_Pau_Monn?= =?utf-8?q?=C3=A9?= " Message-Id: <885867a86eb41fd78df24b6599312b54be8e20ca.1743756934.git.teddy.astie@vates.tech> In-Reply-To: References: X-Native-Encoded: 1 X-Report-Abuse: =?utf-8?q?Please_forward_a_copy_of_this_message=2C_including?= =?utf-8?q?_all_headers=2C_to_abuse=40mandrill=2Ecom=2E_You_can_also_report_?= =?utf-8?q?abuse_here=3A_https=3A//mandrillapp=2Ecom/contact/abuse=3Fid=3D30?= =?utf-8?q?504962=2Ec3e6aab71ed94423bea11c3c0a6a19ba?= X-Mandrill-User: md_30504962 Feedback-ID: 30504962:30504962.20250404:md Date: Fri, 04 Apr 2025 09:49:35 +0000 MIME-Version: 1.0 AMD Translation Cache Extension is a flag that can be enabled in the EFER MSR to optimize some TLB flushes. Expose this flag to guest if supported by hardware. AMD Architecture Developer Manual describe this feature as follow > Setting this bit to 1 changes how the INVLPG, INVLPGB, and INVPCID instructions operate > on TLB entries. When this bit is 0, these instructions remove the target PTE from the > TLB as well as all upper-level table entries that are cached in the TLB, whether or not > they are associated with the target PTE. When this bit is set, these instructions will > remove the target PTE and only those upper-level entries that lead to the target PTE in > the page table hierarchy, leaving unrelated upper-level entries intact. This may provide > a performance benefit. Signed-off-by: Teddy Astie --- CHANGELOG.md | 1 + xen/arch/x86/hvm/hvm.c | 3 +++ xen/arch/x86/include/asm/msr-index.h | 3 ++- xen/include/public/arch-x86/cpufeatureset.h | 1 + 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 8f6afa5c85..dbfecefbd4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -18,6 +18,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) - Support PCI passthrough for HVM domUs when dom0 is PVH (note SR-IOV capability usage is not yet supported on PVH dom0). - Smoke tests for the FreeBSD Xen builds in Cirrus CI. + - Guest support for AMD Translation Cache Extension feature. ### Removed diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 5950f3160f..184357b042 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -959,6 +959,9 @@ const char *hvm_efer_valid(const struct vcpu *v, uint64_t value, if ( (value & EFER_FFXSE) && !p->extd.ffxsr ) return "FFXSE without feature"; + if ( (value & EFER_TCE) && !p->extd.tce ) + return "TCE without feature"; + if ( (value & EFER_AIBRSE) && !p->extd.auto_ibrs ) return "AutoIBRS without feature"; diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index 22d9e76e55..d8576aec1c 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -200,11 +200,12 @@ #define EFER_NXE (_AC(1, ULL) << 11) /* No Execute Enable */ #define EFER_SVME (_AC(1, ULL) << 12) /* Secure Virtual Machine Enable */ #define EFER_FFXSE (_AC(1, ULL) << 14) /* Fast FXSAVE/FXRSTOR */ +#define EFER_TCE (_AC(1, ULL) << 15) /* Translation Cache Extensions */ #define EFER_AIBRSE (_AC(1, ULL) << 21) /* Automatic IBRS Enable */ #define EFER_KNOWN_MASK \ (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE | \ - EFER_AIBRSE) + EFER_TCE | EFER_AIBRSE) #define MSR_STAR _AC(0xc0000081, U) /* legacy mode SYSCALL target */ #define MSR_LSTAR _AC(0xc0000082, U) /* long mode SYSCALL target */ diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index cc6e984a88..8182d2dbed 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -170,6 +170,7 @@ XEN_CPUFEATURE(SKINIT, 3*32+12) /* SKINIT/STGI instructions */ XEN_CPUFEATURE(WDT, 3*32+13) /* Watchdog timer */ XEN_CPUFEATURE(LWP, 3*32+15) /* Light Weight Profiling */ XEN_CPUFEATURE(FMA4, 3*32+16) /*A 4 operands MAC instructions */ +XEN_CPUFEATURE(TCE, 3*32+17) /*H Translation Cache Extension support */ XEN_CPUFEATURE(NODEID_MSR, 3*32+19) /* NodeId MSR */ XEN_CPUFEATURE(TBM, 3*32+21) /*A trailing bit manipulations */ XEN_CPUFEATURE(TOPOEXT, 3*32+22) /* topology extensions CPUID leafs */ From patchwork Fri Apr 4 09:49:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Teddy Astie X-Patchwork-Id: 14038262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F331C36010 for ; Fri, 4 Apr 2025 09:49:54 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.937999.1338827 (Exim 4.92) (envelope-from ) id 1u0dgD-0004pW-F1; Fri, 04 Apr 2025 09:49:41 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 937999.1338827; Fri, 04 Apr 2025 09:49:41 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1u0dgD-0004pP-CV; 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Enable this flag if supported by hardware. Signed-off-by: Teddy Astie --- v2: - Add changelog entry - use trampoline_efer - use cpu_has_tce instead of opencoded boot_cpu_has(X86_FEATURE_TCE) --- CHANGELOG.md | 2 +- xen/arch/x86/include/asm/cpufeature.h | 1 + xen/arch/x86/setup.c | 8 ++++++++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index dbfecefbd4..375905e68a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -18,7 +18,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/) - Support PCI passthrough for HVM domUs when dom0 is PVH (note SR-IOV capability usage is not yet supported on PVH dom0). - Smoke tests for the FreeBSD Xen builds in Cirrus CI. - - Guest support for AMD Translation Cache Extension feature. + - Guest and Xen support for AMD Translation Cache Extension feature. ### Removed diff --git a/xen/arch/x86/include/asm/cpufeature.h b/xen/arch/x86/include/asm/cpufeature.h index 05399fb9c9..ab6d07b767 100644 --- a/xen/arch/x86/include/asm/cpufeature.h +++ b/xen/arch/x86/include/asm/cpufeature.h @@ -114,6 +114,7 @@ static inline bool boot_cpu_has(unsigned int feat) #define cpu_has_xop boot_cpu_has(X86_FEATURE_XOP) #define cpu_has_skinit boot_cpu_has(X86_FEATURE_SKINIT) #define cpu_has_fma4 boot_cpu_has(X86_FEATURE_FMA4) +#define cpu_has_tce boot_cpu_has(X86_FEATURE_TCE) #define cpu_has_tbm boot_cpu_has(X86_FEATURE_TBM) /* CPUID level 0x0000000D:1.eax */ diff --git a/xen/arch/x86/setup.c b/xen/arch/x86/setup.c index d70abb7e0c..0e2e7d012f 100644 --- a/xen/arch/x86/setup.c +++ b/xen/arch/x86/setup.c @@ -2008,6 +2008,14 @@ void asmlinkage __init noreturn __start_xen(void) if ( cpu_has_pku ) set_in_cr4(X86_CR4_PKE); + if ( cpu_has_tce ) + { + printk("Enabling AMD TCE\n"); + + write_efer(read_efer() | EFER_TCE); + trampoline_efer |= EFER_TCE; + } + if ( opt_invpcid && cpu_has_invpcid ) use_invpcid = true;