From patchwork Thu Mar 21 21:44:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 10864389 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 44F3B6C2 for ; Thu, 21 Mar 2019 21:44:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2D85F2A2BB for ; Thu, 21 Mar 2019 21:44:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2137E2A2CC; Thu, 21 Mar 2019 21:44:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AD2CE2A2BB for ; Thu, 21 Mar 2019 21:44:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A89289F99; Thu, 21 Mar 2019 21:44:08 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 677AA89F99 for ; Thu, 21 Mar 2019 21:44:07 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Mar 2019 14:44:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,254,1549958400"; d="scan'208";a="330805995" Received: from invictus.jf.intel.com ([10.54.75.159]) by fmsmga005.fm.intel.com with ESMTP; 21 Mar 2019 14:44:06 -0700 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Thu, 21 Mar 2019 14:44:31 -0700 Message-Id: <20190321214431.515-1-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.20.0.rc2.7.g965798d1f299 In-Reply-To: <20190315221838.22444-1-radhakrishna.sripada@intel.com> References: <20190315221838.22444-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v3] drm/i915/icl: Fix clockgating issue when using scalers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Fixes the clock-gating issue when pipe scaling is enabled. (Lineage #2006604312) V2: Fix typo in headline(Chris) Handle the non double buffered nature of the register(Ville) V3: Fix checkpatch warning. BAT failure for V2 on gen3 looks unrelated. Cc: Chris Wilson Cc: Ville Syrjala Cc: Rodrigo Vivi Cc: Aditya Swarup Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/intel_display.c | 43 +++++++++++++++++----------- 1 file changed, 27 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7c15b428ff84..cfa19ae12e22 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -469,13 +469,22 @@ static const struct intel_limit intel_limits_bxt = { static void skl_wa_clkgate(struct drm_i915_private *dev_priv, int pipe, bool enable) { + u32 val = 0; + + /* + * Wa_2006604312:icl + */ + if (IS_ICELAKE(dev_priv)) + val = DPFR_GATING_DIS; + else + val = DUPS1_GATING_DIS | DUPS2_GATING_DIS; + + /* WA Display #0827: Gen9:all */ if (enable) - I915_WRITE(CLKGATE_DIS_PSL(pipe), - DUPS1_GATING_DIS | DUPS2_GATING_DIS); + I915_WRITE(CLKGATE_DIS_PSL(pipe), val); else I915_WRITE(CLKGATE_DIS_PSL(pipe), - I915_READ(CLKGATE_DIS_PSL(pipe)) & - ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); + I915_READ(CLKGATE_DIS_PSL(pipe)) & ~val); } static bool @@ -5481,14 +5490,18 @@ static bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_s return !old_crtc_state->ips_enabled; } -static bool needs_nv12_wa(struct drm_i915_private *dev_priv, - const struct intel_crtc_state *crtc_state) +static bool skl_needs_clk_wa(struct drm_i915_private *dev_priv, + const struct intel_crtc_state *crtc_state) { - if (!crtc_state->nv12_planes) - return false; - /* WA Display #0827: Gen9:all */ - if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) + if (!!crtc_state->nv12_planes && IS_GEN(dev_priv, 9) && + !IS_GEMINILAKE(dev_priv)) + return true; + + /* + * Wa_2006604312:icl + */ + if (IS_ICELAKE(dev_priv) && crtc_state->pch_pfit.enabled) return true; return false; @@ -5527,9 +5540,8 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) intel_post_enable_primary(&crtc->base, pipe_config); } - /* Display WA 827 */ - if (needs_nv12_wa(dev_priv, old_crtc_state) && - !needs_nv12_wa(dev_priv, pipe_config)) { + if (skl_needs_clk_wa(dev_priv, old_crtc_state) && + !skl_needs_clk_wa(dev_priv, pipe_config)) { skl_wa_clkgate(dev_priv, crtc->pipe, false); } } @@ -5566,9 +5578,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); } - /* Display WA 827 */ - if (!needs_nv12_wa(dev_priv, old_crtc_state) && - needs_nv12_wa(dev_priv, pipe_config)) { + if (!skl_needs_clk_wa(dev_priv, old_crtc_state) && + skl_needs_clk_wa(dev_priv, pipe_config)) { skl_wa_clkgate(dev_priv, crtc->pipe, true); }