From patchwork Thu Apr 10 11:31:02 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 14046423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 614B9C3601E for ; Thu, 10 Apr 2025 11:43:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=MD88gCL7rQbK+pc439u9tVo7TJPofOErBFBWtlbIJ60=; b=EiEsQqQLSfSFKPppQlW8cyFSsl oMTRxi8xEeF7J4sT2iHbapwOXkI/LfwNia6INYMKRxyPaTimjsVGygArAJyIBCKgqkayBJFcdoz8I qHbCrGHo0AQCj1RvfJxDg32wMW/yyzZ6xeHiupC4S5nI1y+w4gcbdkgFDl1enNnwBQvPBxR0rye35 dURfcgigxkuZKwCrINaxHS+ufnvqryEbSuX+1xGrO0RnIk40wZjWftRM2qVfUoZ9bGUau2TmSUrTN a6n7YeSUvpEf8JkaXpWyUJB46wdztddeI8d/6UMotEc03dd3n7oS3dbTRWXaiK/0sZDUgxk+s4p52 /Y5VN+LQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u2qJS-0000000ALIx-1mO2; Thu, 10 Apr 2025 11:43:18 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u2q9k-0000000AJVJ-1MVe for linux-arm-kernel@lists.infradead.org; Thu, 10 Apr 2025 11:33:18 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1744284796; x=1775820796; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=MD88gCL7rQbK+pc439u9tVo7TJPofOErBFBWtlbIJ60=; b=c2hcPStgXMAhpS/ksOFDA63SuAtAoW9Qv/SPPUBGK9DewyNTQQ0wVknV 4knQMBaKbq6TGbCyYZuys4cIzT1IKhq33KnkMfPkXcDHe+U7mI7VXo71P gP/RNSj91Oe+J+pPZ0Q7zZCYeXUfePMtL0Y627FdPH2eAFSQIOjyjgRVV MghoqacEdg4/JeHgiP7e2/63oXCRxRHoxT/+OSv8pWg8Hrv+SNDIZ0E98 nY2JmhGkhhpmtM3vQ5mS3XOgQRDXjIcHWX5mwb+wot+8djVZW5rhwnJqb rSKZad8BUbB7i3uHwPq2KT2QKz+9Qt7AFs0M8/mW03MftO2EjgDMHaBgP g==; X-CSE-ConnectionGUID: ftrXZWfaQzG4fZ8Xgk4A5Q== X-CSE-MsgGUID: GfBzyNicRKeXSWTt2uBJoA== X-IronPort-AV: E=Sophos;i="6.15,202,1739833200"; d="scan'208";a="43454829" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 10 Apr 2025 13:33:11 +0200 X-CheckPoint: {67F7AC77-9-B1D34AC3-DEA5B19F} X-MAIL-CPID: 657CAC6F24C51A7ADDCC0D077348AF1F_4 X-Control-Analysis: str=0001.0A006370.67F7AC82.0092,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EF0641677C0; Thu, 10 Apr 2025 13:33:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1744284786; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=MD88gCL7rQbK+pc439u9tVo7TJPofOErBFBWtlbIJ60=; b=S+Mp5tI6t7kJ68kZ/rvlJx8BpAETCS6IW87/LY6TRHbRBv2J0YSWKKXpn3Bnif0ObnP+iF 9kl5Pi35qEjdIdv2/DABsbTBqSn/IkVNTrygGy35csBEhLPB9VQ+SjJVTeNIj9BzEADMBT u+9lLLJEW5ILPS0CBhnoqu9q5quCRW9+M1neL0SzvMrnphplbgNow2zwjv4cH/mURqm9BI dopeahZjfiRR81vAhSKzYKLN1S11JMUmSN7w90hfjLx7fVCs61ge5QjQFNrB8tNTs9okJC zYI7M0N/wZCp/+mFoFghlrBXPniurliee3paZ614Rz3bjqxltPi/DR9tuPAk9Q== From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Geert Uytterhoeven , Magnus Damm Cc: Alexander Stein , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux@ew.tq-group.com, linux-renesas-soc@vger.kernel.org Subject: [PATCH 1/2] dt: bindings: arm: add bindings for TQMa95xxSA Date: Thu, 10 Apr 2025 13:31:02 +0200 Message-ID: <20250410113107.2057426-1-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250410_043316_848062_30686E76 X-CRM114-Status: UNSURE ( 7.28 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org TQMa95xxSA is a SOM using NXP i.MX95 CPU. MB-SMARC-2 is a carrier reference design. [1] https://www.tq-group.com/en/products/tq-embedded/arm-architecture/tqma95xxsa/ Signed-off-by: Alexander Stein Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/fsl.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 1b90870958a22..0ce2653066e91 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1403,6 +1403,16 @@ properties: - const: kontron,imx93-osm-s # Kontron OSM-S i.MX93 SoM - const: fsl,imx93 + - description: + TQMa95xxSA is a series of SOM featuring NXP i.MX95 SoC variants. + It has the SMARC form factor and is designed to be placed on + different carrier boards. MB-SMARC-2 is a carrier reference design. + items: + - enum: + - tq,imx95-tqma9596sa-mb-smarc-2 # TQ-Systems GmbH i.MX95 TQMa95xxSA SOM on MB-SMARC-2 + - const: tq,imx95-tqma9596sa # TQ-Systems GmbH i.MX95 TQMa95xxSA SOM + - const: fsl,imx95 + - description: Freescale Vybrid Platform Device Tree Bindings From patchwork Thu Apr 10 11:31:03 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Stein X-Patchwork-Id: 14046437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E588C3601E for ; Thu, 10 Apr 2025 11:45:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BQN2eF3zgJqeni5K47dKLL1IPlt0dyuRcNUzRPqmPVQ=; b=Bdw0TLD1Kp6ppdhydPenOJPpGd h4I++ZzY0y8EA1QbprOGM7RaeoV+n7dHSP0XtJ2YkUMIuQAhb/oLi4cvDlAlkf7l1HJtk3rqUsp8z 1ogiXD97KdiaWNXV2crpEDR/M9iRYwitH5ljOxpC7eHZ7188IJAbI6+yBj0Kwy8RMMDLFR034nGNp urH11q9V4YX1ANR+HuBu4/UPSInJwTDe0BzZYFuDEd4f5Z9fOp9m4fVC9YatXM2mTgqvtqS5Bc4DB NPJFNtqZBVy1BmQDCJWueTqTSOeE5y7LTdJ/60gMvzHWQQVlKJeN4ORbXIYD+YA5/8xVBp4Mo3xWA u6cDcORw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u2qLD-0000000ALfB-12FE; Thu, 10 Apr 2025 11:45:07 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u2q9p-0000000AJVJ-0jTq for linux-arm-kernel@lists.infradead.org; Thu, 10 Apr 2025 11:33:23 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1744284801; x=1775820801; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BQN2eF3zgJqeni5K47dKLL1IPlt0dyuRcNUzRPqmPVQ=; b=ZY2Y5fZtVOaj7Sfuyc0Z5DbVA8jFCGdhK5fasXpYLX/JwoB+89nsSO5d kcS3KmaHwcdxbKeiRaJFIipLqu05qIe6oXvhKzEOJ7AmMtHPH5mMxQL1p G5y03mPyTNF2KYdUOoet2hWAA3LClgL08QZyZUf0TsdvdM5lNxH3YMbaT te+3vv2TK+3Rf/x8dqFbblsYsJVe65uVEZX7hkzJ24zToDnLpnD742Xp9 t4O8VilRMAMuVHLd86sdZeXPj1d6ykbGv+PmsdiCeC5uoT3AeDUh0wL6B 9elwkNBoJ+yEHjDihTRn2LyF03efsYgiCnDXorVNGHBMqFy87/nrxMolX w==; X-CSE-ConnectionGUID: aE/4wSSlSR28TBVdsMD4rA== X-CSE-MsgGUID: PiFw3VCvRw6Gr96befCWGg== X-IronPort-AV: E=Sophos;i="6.15,202,1739833200"; d="scan'208";a="43454836" Received: from vmailcow01.tq-net.de ([10.150.86.48]) by mx1.tq-group.com with ESMTP; 10 Apr 2025 13:33:18 +0200 X-CheckPoint: {67F7AC7D-1F-2417938-F0170C2B} X-MAIL-CPID: 5C570CC9BBC12D20EEA40C94E8760BAD_2 X-Control-Analysis: str=0001.0A006374.67F7AC71.0051,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B9F6D1689D2; Thu, 10 Apr 2025 13:33:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ew.tq-group.com; s=dkim; t=1744284793; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BQN2eF3zgJqeni5K47dKLL1IPlt0dyuRcNUzRPqmPVQ=; b=gttDr2m22c5/BqIIqU1eoy5TKGgsUez4+oy7qVG4erMiI3SfFdNMOM+WbdWasfwPBpQes4 Ve1d76r4Oei7jGvHKsA76lo2fQpfV4pRaD8LY8S3ElHumB5Vh4BgCFjYSdLkWNqCRX2fgp oT2nvnJmHzMv3JPhtDLYpBIUTl8sfBmyxSXU/Aa8W1uPiWuMIcO9saHt3r2DdLbowcVpaj /ddW8R20yDMX+gGzT3DAZBEKMZeNDLK76l2Tsk4LkKCrjdbm3v9e3fIr7Cvrl4lcC9+RDt G0+wMVL74rwJcXvQAy0Yge3vRw9PSW3oxn0COIjucRdLLCYiYBx/nDyMm5O+wA== From: Alexander Stein To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Geert Uytterhoeven , Magnus Damm Cc: Alexander Stein , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux@ew.tq-group.com, linux-renesas-soc@vger.kernel.org Subject: [PATCH 2/2] arm64: dt: imx95: Add TQMa95xxSA Date: Thu, 10 Apr 2025 13:31:03 +0200 Message-ID: <20250410113107.2057426-2-alexander.stein@ew.tq-group.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250410113107.2057426-1-alexander.stein@ew.tq-group.com> References: <20250410113107.2057426-1-alexander.stein@ew.tq-group.com> MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250410_043321_677409_4BB9AA6B X-CRM114-Status: GOOD ( 14.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add initial support for TQMa95xxSA module compatible to SMARC-2. There is a common device tree for all variants with e.g. reduced CPU count. It supports LPUART7 for console, CAN, PCIe I2C, SPI, USB3.0, Audio, SDHC1/2 and QSPI as storage. [1] https://www.tq-group.com/en/products/tq-embedded/arm-architecture/tqma95xxsa/ Signed-off-by: Alexander Stein --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../freescale/imx95-tqma9596sa-mb-smarc-2.dts | 314 ++++++++ .../boot/dts/freescale/imx95-tqma9596sa.dtsi | 698 ++++++++++++++++++ 3 files changed, 1013 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts create mode 100644 arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index b6d3fe26d6212..d23cce37aa2d7 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -303,6 +303,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts new file mode 100644 index 0000000000000..1af72b5b7e35f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa-mb-smarc-2.dts @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include +#include "imx95-tqma9596sa.dtsi" + +/ { + model = "TQ-Systems i.MX95 TQMa95xxSA on MB-SMARC-2"; + compatible = "tq,imx95-tqma9596sa-mb-smarc-2", "tq,imx95-tqma9596sa", "fsl,imx95"; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &lpi2c1; + i2c1 = &lpi2c2; + i2c2 = &lpi2c3; + i2c3 = &lpi2c4; + i2c4 = &lpi2c5; + i2c5 = &lpi2c6; + i2c6 = &lpi2c7; + i2c7 = &lpi2c8; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &pcf85063; + rtc1 = &scmi_bbm; + serial0 = &lpuart1; + serial1 = &lpuart2; + serial2 = &lpuart3; + serial3 = &lpuart4; + serial4 = &lpuart5; + serial5 = &lpuart6; + serial6 = &lpuart7; + serial7 = &lpuart8; + }; + + chosen { + stdout-path = &lpuart7; + }; + + backlight_lvds0: backlight-lvds0 { + compatible = "pwm-backlight"; + pwms = <&tpm3 0 100000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>; + power-supply = <®_12v0>; + status = "disabled"; + }; + + backlight_lvds1: backlight-lvds1 { + compatible = "pwm-backlight"; + pwms = <&tpm4 0 100000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>; + power-supply = <®_12v0>; + status = "disabled"; + }; + + panel_lvds0: panel-lvds0 { + /* + * Display is not fixed, so compatible has to be added from + * DT + */ + backlight = <&backlight_lvds0>; + power-supply = <®_lvds0>; + status = "disabled"; + + port { + panel_in_lvds0: endpoint { + // TODO: LVDS0 out + }; + }; + }; + + panel_lvds1: panel-lvds1 { + /* + * Display is not fixed, so compatible has to be added from + * DT + */ + backlight = <&backlight_lvds1>; + power-supply = <®_lvds1>; + status = "disabled"; + + port { + panel_in_lvds1: endpoint { + // TODO: LVDS1 out + }; + }; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "12V0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_lvds0: regulator-lvds0 { + compatible = "regulator-fixed"; + regulator-name = "LCD0_VDD_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander2 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds1: regulator-lvds1 { + compatible = "regulator-fixed"; + regulator-name = "LCD1_VDD_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander2 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; + audio-codec = <&tlv320aic3x04>; + audio-cpu = <&sai3>; + }; +}; + +&enetc_port0 { + status = "okay"; +}; + +&enetc_port1 { + status = "okay"; +}; + +&expander2 { + pcie1-clk-en-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE1_CLK_EN"; + }; + + pcie2-clk-en-hog { + gpio-hog; + gpios = <15 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCIE2_CLK_EN"; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&lpi2c1 { + tlv320aic3x04: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; + clock-names = "mclk"; + iov-supply = <®_1v8>; + ldoin-supply = <®_3v3>; + }; + + eeprom2: eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_3v3>; + }; +}; + +&lpspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + cs-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* SER0 */ +&lpuart1 { + status = "disabled"; +}; + +/* SER3 */ +&lpuart5 { + status = "okay"; +}; + +/* SER1 */ +&lpuart7 { + status = "okay"; +}; + +/* SER2 */ +&lpuart8 { + status = "okay"; +}; + +/* X44 mPCIe */ +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&pcieclk 1>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + reset-gpio = <&expander2 9 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* X22 PCIe x1 socket */ +&pcie1 { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&pcieclk 0>, + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + reset-gpio = <&expander2 10 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +®_sdvmmc { + status = "okay"; +}; + +&sai3 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai5 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI5>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; +}; + +/* TODO: USB2 */ + +/* X16 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2>; + vmmc-supply = <®_sdvmmc>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + no-mmc; + no-sdio; + disable-wp; + bus-width = <4>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi new file mode 100644 index 0000000000000..3fcd7bb2b0ee5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx95-tqma9596sa.dtsi @@ -0,0 +1,698 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include +#include +#include +#include "imx95.dtsi" + +/ { + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + }; + + memory@80000000 { + device_type = "memory"; + /* + * DRAM base addr, size : 2048 MiB DRAM + * should be corrected by bootloader + */ + reg = <0 0x80000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + alloc-ranges = <0 0x80000000 0 0x80000000>; + linux,cma-default; + }; + + vpu_boot: vpu_boot@a0000000 { + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; + }; + + clk_dp: clk-dp { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + reg_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* Controlled by system manager */ + reg_sdvmmc: regulator-sdvmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdvmmc>; + regulator-name = "SDIO_PWR_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; +}; + +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; +}; + +&enetc_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc1>; + phy-handle = <ðphy3>; + phy-mode = "rgmii-id"; +}; + +&netc_timer { + status = "okay"; +}; + +&flexspi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexspi1>; + pinctrl-1 = <&pinctrl_flexspi1>; + status = "okay"; + + flash0: flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + vcc-supply = <®_1v8>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "GPIO7", "GPIO8", + "", "GPIO9", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>; + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "SLEEP", "GPIO5", + "", "", "GPIO6", "", + "", "", "", "", + "", "", "", ""; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + tmp1075: temperature-sensor@4a { + compatible = "ti,tmp1075"; + reg = <0x4a>; + vs-supply = <®_1v8>; + }; + + eeprom_smarc: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <®_1v8>; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf85063>; + interrupt-parent = <&gpio2>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + }; + + m24c64: eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + vcc-supply = <®_1v8>; + }; + + /* protectable identification memory (part of M24C64-D @50) */ + eeprom@58 { + compatible = "atmel,24c64d-wl"; + reg = <0x58>; + vcc-supply = <®_1v8>; + }; + + /* protectable identification memory (part of M24C64-D @54) */ + eeprom@5c { + compatible = "atmel,24c64d-wl"; + reg = <0x5c>; + vcc-supply = <®_1v8>; + }; + + pcieclk: clock-generator@6a { + compatible = "renesas,9fgv0441"; + reg = <0x6a>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; + + imu@6b { + compatible = "st,ism330dhcx"; + reg = <0x6b>; + vdd-supply = <®_3v3>; + vddio-supply = <®_3v3>; + }; + + /* D23 */ + expander2: gpio@74 { + compatible = "ti,tca9539"; + reg = <0x74>; + vcc-supply = <®_1v8>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO4", "LCD0_BLKT_EN", "LCD0_VDD_EN", "LCD1_BLKT_EN", + "LCD1_VDD_EN", "ENET1_RESET#", "ENET2_RESET#", "GBE0_SDP_DIR", + "GBE1_SDP_DIR", "PCIE1_RST#", "PCIE2_RST#", "DP_BRIDGE_EN", + "HUB_RST#", "QSPI_RESET#", "PCIE1_CLK_EN", "PCIE2_CLK_EN"; + }; + + /* D21 */ + expander1: gpio@75 { + compatible = "ti,tca9539"; + reg = <0x75>; + vcc-supply = <®_1v8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_expander1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + gpio-line-names = "GPIO10", "GPIO11", "GPIO12", "GPIO13", + "CHG_PRSNT#", "CHARGING", "LID", "BATLOW#", + "TEMP_EVENT#", "PGOOD_ARM", "PGOOD_SOC", "PCIE_WAKE#_1V8", + "GPIO0", "GPIO1", "GPIO2", "GPIO3"; + }; +}; + +/* I2C_CAM0 */ +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + dp_bridge: dp-bridge@f { + compatible = "toshiba,tc9595", "toshiba,tc358767"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tc9595>; + clock-names = "ref"; + clocks = <&clk_dp>; + reset-gpios = <&expander2 11 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio2>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + toshiba,hpd-pin = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dp_dsi_in: endpoint { + // TODO: DSI out + data-lanes = <1 2 3 4>; + }; + }; + }; + }; +}; + +/* I2C_CAM1 */ +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4>; + status = "okay"; +}; + +/* I2C_LCD */ +&lpi2c6 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c6>; + pinctrl-1 = <&pinctrl_lpi2c6>; + status = "okay"; +}; + +/* SER0 */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; +}; + +/* SER3 */ +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart5>; +}; + +/* SER1 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart7>; +}; + +/* SER2 */ +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart8>; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio>; + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy0>; + reset-gpios = <&expander2 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio5>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; + + ethphy3: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ethphy3>; + reset-gpios = <&expander2 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = ; + }; +}; + +&scmi_bbm { + linux,code = ; +}; + +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm3>; +}; + +&tpm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm4>; +}; + +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&expander2 12 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&expander2 12 GPIO_ACTIVE_LOW>; + vdd-supply = <®_3v3>; + }; +}; + +&usb3_phy { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_ethphy0: ethphy0grp { + fsl,pins = ; + }; + + pinctrl_ethphy3: ethphy3grp { + fsl,pins = ; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_expander1: expander1grp { + fsl,pins = ; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = , + ; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = , + ; + }; + + pinctrl_flexspi1: flexspi1grp { + fsl,pins = , + , + , + , + , + ; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = , + , + ; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = , + , + ; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = , + ; + }; + + pinctrl_lpi2c6: lpi2c6grp { + fsl,pins = , + ; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_lpuart5: lpuart5grp { + fsl,pins = , + ; + }; + + pinctrl_lpuart7: lpuart7grp { + fsl,pins = , + ; + }; + + pinctrl_lpuart8: lpuart8grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_mdio: mdiogrp { + fsl,pins = , + ; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins = ; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = ; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = ; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = , + , + , + , + ; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = , + , + , + ; + }; + + pinctrl_sdvmmc: sdvmmcgrp { + fsl,pins = ; + }; + + pinctrl_tc9595: tc9595grp { + fsl,pins = ; + }; + + pinctrl_tpm3: tpm3grp { + fsl,pins = ; + }; + + pinctrl_tpm4: tpm4grp { + fsl,pins = ; + }; + + pinctrl_tpm5: tpm4grp { + fsl,pins = ; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = , + , + , + , + , + , + , + ; + }; +};