From patchwork Fri Mar 22 10:43:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pu Wen X-Patchwork-Id: 10865493 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E7ACF14DE for ; Fri, 22 Mar 2019 10:47:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C9E692A65B for ; Fri, 22 Mar 2019 10:47:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B98102A672; Fri, 22 Mar 2019 10:47:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 29DB72A65B for ; Fri, 22 Mar 2019 10:47:33 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1h7Hfw-0001su-Og; Fri, 22 Mar 2019 10:45:24 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1h7Hfu-0001sj-Pm for xen-devel@lists.xenproject.org; Fri, 22 Mar 2019 10:45:22 +0000 X-Inumbo-ID: 9510f456-4c8f-11e9-bc90-bc764e045a96 Received: from spam1.hygon.cn (unknown [110.188.70.11]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 9510f456-4c8f-11e9-bc90-bc764e045a96; Fri, 22 Mar 2019 10:45:19 +0000 (UTC) Received: from MK-DB.hygon.cn ([172.23.18.60]) by spam1.hygon.cn with ESMTP id x2MAiOqx042826; Fri, 22 Mar 2019 18:44:24 +0800 (GMT-8) (envelope-from puwen@hygon.cn) Received: from cncheex01.Hygon.cn ([172.23.18.10]) by MK-DB.hygon.cn with ESMTP id x2MAiHGn064391; Fri, 22 Mar 2019 18:44:17 +0800 (GMT-8) (envelope-from puwen@hygon.cn) Received: from pw-vbox.hygon.cn (172.23.18.44) by cncheex01.Hygon.cn (172.23.18.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1466.3; Fri, 22 Mar 2019 18:44:21 +0800 From: Pu Wen To: , , , , , , Date: Fri, 22 Mar 2019 18:43:39 +0800 Message-ID: <1553251419-7066-1-git-send-email-puwen@hygon.cn> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [172.23.18.44] X-ClientProxiedBy: cncheex02.Hygon.cn (172.23.18.12) To cncheex01.Hygon.cn (172.23.18.10) X-MAIL: spam1.hygon.cn x2MAiOqx042826 X-DNSRBL: Subject: [Xen-devel] [RFC PATCH] x86/xen/pmu: Use MSRs C001_020X instead of the legacy MSRs for Hygon X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org, Pu Wen Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP The Hygon Dhyana processor supports MSRs C001_020X for the performance monitor counter(PMC). There are six core performance events counters for Dhyana but there are only four legacy PMC MSRs. So switching to use MSRs C001_020X(compatible with the F15H ones) for Xen vPMU infrastructure on Hygon platform. Signed-off-by: Pu Wen --- arch/x86/xen/pmu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index e13b0b4..6480eed 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -92,11 +92,11 @@ static void xen_pmu_arch_init(void) break; } } else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) { - amd_num_counters = F10H_NUM_COUNTERS; - amd_counters_base = MSR_K7_PERFCTR0; - amd_ctrls_base = MSR_K7_EVNTSEL0; - amd_msr_step = 1; - k7_counters_mirrored = 0; + amd_num_counters = F15H_NUM_COUNTERS; + amd_counters_base = MSR_F15H_PERF_CTR; + amd_ctrls_base = MSR_F15H_PERF_CTL; + amd_msr_step = 2; + k7_counters_mirrored = 1; } else { uint32_t eax, ebx, ecx, edx;