From patchwork Wed Apr 16 06:27:30 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 14053228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E56ADC369BA for ; Wed, 16 Apr 2025 06:29:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6BD7210E835; Wed, 16 Apr 2025 06:29:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="c4h8Q/bC"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6788910E835 for ; Wed, 16 Apr 2025 06:29:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744784988; x=1776320988; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=4kRoIDYBIs81VT8t8t29C8/ilyejerXO1Cfu7X5/CqA=; b=c4h8Q/bC7AYMJp8mWL0cV+BwH2jg2yYrw9WUg7kCO8mT7aGwJ/cm8N2T mUCVEYsKVspwVUHGz1Q8BiROsBXLMUPR8QaH7qfEtgKZw2lAExoImuqxc VCszuWbkMLhUe74nZ7/ElRUqjFnKe60mo7wi9MhAR/Y82ZS09uCueOjV6 H14VqqswQdeIA/SIpGxwQ8qQpj9+GajWMEM1hXqD0rC+fSUNkZg6ncB1O 2vXnJ8SXuR0h1cJio1cnxR/gqBnFIZ1q8y1ChIkVEblu7Vv9kxPQIXrpo q+t9Zrybz8YW2X07imsf214+gHCiDzCKl9VzTGOmb2vL3Fq/Fuiv6dGJc w==; X-CSE-ConnectionGUID: o0gAiiUNTWCG8l1mJ6+7NQ== X-CSE-MsgGUID: hnVWOR6ZRXW5lXUc9ndvMQ== X-IronPort-AV: E=McAfee;i="6700,10204,11404"; a="71710241" X-IronPort-AV: E=Sophos;i="6.15,215,1739865600"; d="scan'208";a="71710241" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 23:29:48 -0700 X-CSE-ConnectionGUID: gzsI6M2MQ5aX8fNiA2j3vw== X-CSE-MsgGUID: U7yZCJxlTwC68Tl4/Ngdtw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,215,1739865600"; d="scan'208";a="130880167" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa007.jf.intel.com with ESMTP; 15 Apr 2025 23:29:46 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Subject: [PATCH v1 1/8] drm/i915/vrr: Add DC balance registers Date: Wed, 16 Apr 2025 11:57:30 +0530 Message-ID: <20250416062737.1766703-2-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> References: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add register to access DC Balance registers. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr_regs.h | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h index 6ed0e0dc97e7..6297108f1357 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h @@ -9,6 +9,20 @@ #include "intel_display_reg_defs.h" /* VRR registers */ +#define _TRANS_VRR_VMAX_DCB_A 0x60414 /* lnl+ */ +#define _TRANS_VRR_VMAX_DCB_B 0x61414 /* lnl+ */ +#define TRANS_VRR_VMAX_DCB(trans) _MMIO_TRANS((trans), \ + _TRANS_VRR_VMAX_DCB_A, \ + _TRANS_VRR_VMAX_DCB_B) +#define VRR_VMAX_DCB_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_FLIPLINE_DCB_A 0x60418 /* lnl+ */ +#define _TRANS_VRR_FLIPLINE_DCB_B 0x61418 /* lnl+ */ +#define TRANS_VRR_FLIPLINE_DCB(trans) _MMIO_TRANS((trans), \ + _TRANS_VRR_FLIPLINE_DCB_A, \ + _TRANS_VRR_FLIPLINE_DCB_B) +#define VRR_FLIPLINE_DCB_MASK REG_GENMASK(19, 0) + #define _TRANS_VRR_CTL_A 0x60420 #define _TRANS_VRR_CTL_B 0x61420 #define _TRANS_VRR_CTL_C 0x62420 @@ -17,6 +31,7 @@ #define VRR_CTL_VRR_ENABLE REG_BIT(31) #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) +#define VRR_CTL_DCB_ADJ_ENABLE REG_BIT(28) /* lnl+ */ #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) @@ -93,6 +108,34 @@ #define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A) #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A 0x604c0 /* lnl+ */ +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B 0x614c0 /* lnl+ */ +#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans) _MMIO_TRANS((trans), \ + _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \ + _TRANS_ADAPTIVE_SYNC_DCB_CTL_B) +#define ADAPTIVE_SYNC_COUNTER_EN REG_BIT(31) +#define ADAPTIVE_SYNC_COUNTER_RESET REG_BIT(30) +#define ADAPTIVE_SYNC_ODD_COUNTER_OVERFLOW REG_BIT(15) +#define ADAPTIVE_SYNC_EVEN_COUNTER_OVERFLOW REG_BIT(14) +#define ADAPTIVE_SYNC_ODD_LINE_COUNTER_OVERFLOW REG_BIT(13) +#define ADAPTIVE_SYNC_EVEN_LINE_COUNTER_OVERFLOW REG_BIT(12) + +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A 0x604d4 /* lnl+ */ +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B 0x614d4 /* lnl+ */ +#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans) _MMIO_TRANS((trans), \ + _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \ + _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B) +#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK REG_GENMASK(31, 24) +#define VRR_DCB_ADJ_FLIPLINE_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A 0x604d8 /* lnl+ */ +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B 0x614d8 /* lnl+ */ +#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans) _MMIO_TRANS((trans), \ + _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \ + _TRANS_VRR_DCB_ADJ_VMAX_CFG_B) +#define VRR_DCB_ADJ_VMAX_CNT_MASK REG_GENMASK(31, 24) +#define VRR_DCB_ADJ_VMAX_MASK REG_GENMASK(19, 0) + #define _TRANS_PUSH_A 0x60a70 #define _TRANS_PUSH_B 0x61a70 #define _TRANS_PUSH_C 0x62a70 From patchwork Wed Apr 16 06:27:31 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 14053231 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10660C369C1 for ; Wed, 16 Apr 2025 06:29:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7359B10E836; Wed, 16 Apr 2025 06:29:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="lCE9D0YU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3174A10E835 for ; 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15 Apr 2025 23:29:49 -0700 X-CSE-ConnectionGUID: JXANON9fQ8qarLLmFtVc2w== X-CSE-MsgGUID: YCjmA4D0Rza5G3zeBCnZZg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,215,1739865600"; d="scan'208";a="130880175" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa007.jf.intel.com with ESMTP; 15 Apr 2025 23:29:47 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Subject: [PATCH v1 2/8] drm/i915/dmc: Add pipe DMC DC balance registers Date: Wed, 16 Apr 2025 11:57:31 +0530 Message-ID: <20250416062737.1766703-3-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> References: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add pipe registers to access pipe DMC DC Balance registers. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dmc_regs.h | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h index 1bf446f96a10..5ac409fbbc4e 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h @@ -103,4 +103,41 @@ #define DMC_WAKELOCK_CTL_REQ REG_BIT(31) #define DMC_WAKELOCK_CTL_ACK REG_BIT(15) +#define _PIPEDMC_DCB_CTL_A 0x5f1a0 +#define _PIPEDMC_DCB_CTL_B 0x5f5a0 +#define PIPEDMC_DCB_CTL(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_CTL_A, _PIPEDMC_DCB_CTL_B) +#define PIPEDMC_ADAPTIVE_DCB_ENABLE REG_BIT(31) + +#define _PIPEDMC_DCB_VMIN_A 0x5f1a4 +#define _PIPEDMC_DCB_VMIN_B 0x5f5a4 +#define PIPEDMC_DCB_VMIN(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMIN_A, _PIPEDMC_DCB_VMIN_B) + +#define _PIPEDMC_DCB_VMAX_A 0x5f1a8 +#define _PIPEDMC_DCB_VMAX_B 0x5f5a8 +#define PIPEDMC_DCB_VMAX(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMAX_A, _PIPEDMC_DCB_VMAX_B) + +#define _PIPEDMC_DCB_MAX_INCREASE_A 0x5f1ac +#define _PIPEDMC_DCB_MAX_INCREASE_B 0x5f5ac +#define PIPEDMC_DCB_MAX_INCREASE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_INCREASE_A, _PIPEDMC_DCB_MAX_INCREASE_B) + +#define _PIPEDMC_DCB_MAX_DECREASE_A 0x5f1b0 +#define _PIPEDMC_DCB_MAX_DECREASE_B 0x5f5b0 +#define PIPEDMC_DCB_MAX_DECREASE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_DECREASE_A, _PIPEDMC_DCB_MAX_DECREASE_B) + +#define _PIPEDMC_DCB_GUARDBAND_A 0x5f1b4 +#define _PIPEDMC_DCB_GUARDBAND_B 0x5f5b4 +#define PIPEDMC_DCB_GUARDBAND(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_GUARDBAND_A, _PIPEDMC_DCB_GUARDBAND_B) + +#define _PIPEDMC_DCB_SLOPE_A 0x5f1b8 +#define _PIPEDMC_DCB_SLOPE_B 0x5f5b8 +#define PIPEDMC_DCB_SLOPE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_SLOPE_A, _PIPEDMC_DCB_SLOPE_B) + +#define _PIPEDMC_DCB_VBLANK_A 0x5f1bc +#define _PIPEDMC_DCB_VBLANK_B 0x5f5bc +#define PIPEDMC_DCB_VBLANK(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VBLANK_A, _PIPEDMC_DCB_VBLANK_B) + +#define _PIPEDMC_DCB_DEBUG_A 0x5f1c0 +#define _PIPEDMC_DCB_DEBUG_B 0x5f5c0 +#define PIPEDMC_DCB_DEBUG(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_DEBUG_A, _PIPEDMC_DCB_DEBUG_B) + #endif /* __INTEL_DMC_REGS_H__ */ From patchwork Wed Apr 16 06:27:32 2025 Content-Type: text/plain; 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15 Apr 2025 23:29:50 -0700 X-CSE-ConnectionGUID: UQxjqYEoSTqXOrSriJ8e1w== X-CSE-MsgGUID: vCs03yDZQD6bmCW7WK+Xug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,215,1739865600"; d="scan'208";a="130880178" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa007.jf.intel.com with ESMTP; 15 Apr 2025 23:29:49 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Subject: [PATCH v1 3/8] drm/i915/vrr: Refactor vmin/vmax stuff Date: Wed, 16 Apr 2025 11:57:32 +0530 Message-ID: <20250416062737.1766703-4-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> References: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Refactor vmin/vmax functions for better computation. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 42 +++++++++++------------- 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index c6565baf815a..afa1728837d2 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -146,37 +146,42 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1; } -int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state) +static int intel_vrr_vtotal(const struct intel_crtc_state *crtc_state, int vmin_vmax) { struct intel_display *display = to_intel_display(crtc_state); - /* Min vblank actually determined by flipline */ if (DISPLAY_VER(display) >= 13) - return intel_vrr_vmin_flipline(crtc_state); + return vmin_vmax; else - return intel_vrr_vmin_flipline(crtc_state) + - intel_vrr_real_vblank_delay(crtc_state); + return vmin_vmax + intel_vrr_real_vblank_delay(crtc_state); } -int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state) + +static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state, + int vmin_vmax) { - struct intel_display *display = to_intel_display(crtc_state); + return intel_vrr_vtotal(crtc_state, vmin_vmax) - + intel_vrr_vblank_exit_length(crtc_state); +} - if (DISPLAY_VER(display) >= 13) - return crtc_state->vrr.vmax; - else - return crtc_state->vrr.vmax + - intel_vrr_real_vblank_delay(crtc_state); +int intel_vrr_vmin_vtotal(const struct intel_crtc_state *crtc_state) +{ + return intel_vrr_vtotal(crtc_state, intel_vrr_vmin_flipline(crtc_state)); +} + +int intel_vrr_vmax_vtotal(const struct intel_crtc_state *crtc_state) +{ + return intel_vrr_vtotal(crtc_state, crtc_state->vrr.vmax); } int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state) { - return intel_vrr_vmin_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state); + return intel_vrr_vblank_start(crtc_state, intel_vrr_vmin_flipline(crtc_state)); } int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) { - return intel_vrr_vmax_vtotal(crtc_state) - intel_vrr_vblank_exit_length(crtc_state); + return intel_vrr_vblank_start(crtc_state, crtc_state->vrr.vmax); } static bool @@ -257,14 +262,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state) static int intel_vrr_fixed_rr_vtotal(const struct intel_crtc_state *crtc_state) { - struct intel_display *display = to_intel_display(crtc_state); - int crtc_vtotal = crtc_state->hw.adjusted_mode.crtc_vtotal; - - if (DISPLAY_VER(display) >= 13) - return crtc_vtotal; - else - return crtc_vtotal - - intel_vrr_real_vblank_delay(crtc_state); + return intel_vrr_vtotal(crtc_state, crtc_state->hw.adjusted_mode.crtc_vtotal); } static From patchwork Wed Apr 16 06:27:33 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 14053227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E176EC369B1 for ; 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X-CSE-ConnectionGUID: AlM5EVTpRR+3d4TNkgeNQw== X-CSE-MsgGUID: vhz+dwTUQ6O9Nrm5aI9Ogg== X-IronPort-AV: E=McAfee;i="6700,10204,11404"; a="71710246" X-IronPort-AV: E=Sophos;i="6.15,215,1739865600"; d="scan'208";a="71710246" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 23:29:51 -0700 X-CSE-ConnectionGUID: hCYWSsP+QuOOLZKWhFdt2A== X-CSE-MsgGUID: tTgz88yzQ/C8wn3IUtqDsw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,215,1739865600"; d="scan'208";a="130880187" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa007.jf.intel.com with ESMTP; 15 Apr 2025 23:29:50 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Subject: [PATCH v1 4/8] drm/i915/vrr: Add functions to read out vmin/vmax stuff Date: Wed, 16 Apr 2025 11:57:33 +0530 Message-ID: <20250416062737.1766703-5-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> References: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Calculate delayed vblank start position with the help of added vmin/vmax stuff for next frame and final computation. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vrr.c | 55 +++++++++++++++++++++++- drivers/gpu/drm/i915/display/intel_vrr.h | 5 +++ 2 files changed, 59 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index afa1728837d2..03405c274b8c 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -156,7 +156,6 @@ static int intel_vrr_vtotal(const struct intel_crtc_state *crtc_state, int vmin_ return vmin_vmax + intel_vrr_real_vblank_delay(crtc_state); } - static int intel_vrr_vblank_start(const struct intel_crtc_state *crtc_state, int vmin_vmax) { @@ -747,3 +746,57 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) if (crtc_state->vrr.enable) crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } + +int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 tmp; + + tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder)); + + if (REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_CNT_MASK, tmp) == 0) + return -1; + + return intel_vrr_vblank_start(crtc_state, + REG_FIELD_GET(VRR_DCB_ADJ_FLIPLINE_MASK, tmp) + 1); +} + +int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 tmp; + + tmp = intel_de_read(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder)); + + if (REG_FIELD_GET(VRR_DCB_ADJ_VMAX_CNT_MASK, tmp) == 0) + return -1; + + return intel_vrr_vblank_start(crtc_state, + REG_FIELD_GET(VRR_DCB_ADJ_VMAX_MASK, tmp) + 1); +} + +int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 tmp; + + tmp = intel_de_read(display, TRANS_VRR_FLIPLINE_DCB(cpu_transcoder)); + + return intel_vrr_vblank_start(crtc_state, + REG_FIELD_GET(VRR_FLIPLINE_DCB_MASK, tmp) + 1); +} + +int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 tmp; + + tmp = intel_de_read(display, TRANS_VRR_VMAX_DCB(cpu_transcoder)); + + return intel_vrr_vblank_start(crtc_state, + REG_FIELD_GET(VRR_VMAX_DCB_MASK, tmp) + 1); +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h index 38bf9996b883..e62b8b50aec6 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h @@ -42,4 +42,9 @@ void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state); bool intel_vrr_always_use_vrr_tg(struct intel_display *display); +int intel_vrr_dcb_vmin_vblank_start_next(const struct intel_crtc_state *crtc_state); +int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_state); +int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state); +int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state); + #endif /* __INTEL_VRR_H__ */ From patchwork Wed Apr 16 06:27:34 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 14053232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E193DC369BA for ; Wed, 16 Apr 2025 06:29:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4439B10E83A; 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X-CSE-ConnectionGUID: SFunMnQgT0mStVw1pwvOHw== X-CSE-MsgGUID: /MCT/yrXQ4iVe1ELtmyXdA== X-IronPort-AV: E=McAfee;i="6700,10204,11404"; a="71710252" X-IronPort-AV: E=Sophos;i="6.15,215,1739865600"; d="scan'208";a="71710252" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 23:29:52 -0700 X-CSE-ConnectionGUID: HcIKjINaRMufWfMmKYfS1g== X-CSE-MsgGUID: wNLJbuNgTqW9N87FbfNvYQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,215,1739865600"; d="scan'208";a="130880198" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa007.jf.intel.com with ESMTP; 15 Apr 2025 23:29:51 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Subject: [PATCH v1 5/8] drm/i915: Extract vrr_vblank_start() Date: Wed, 16 Apr 2025 11:57:34 +0530 Message-ID: <20250416062737.1766703-6-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> References: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Initialise delayed vblank position for evasion logic. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_vblank.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 139fa5deba80..680013f00fc0 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -642,6 +642,14 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state, return pre_commit_crtc_state(old_crtc_state, new_crtc_state); } +static int vrr_vblank_start(const struct intel_crtc_state *crtc_state) +{ + if (intel_vrr_is_push_sent(crtc_state)) + return intel_vrr_vmin_vblank_start(crtc_state); + else + return intel_vrr_vmax_vblank_start(crtc_state); +} + void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state, struct intel_vblank_evade_ctx *evade) @@ -668,10 +676,7 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) || new_crtc_state->update_m_n || new_crtc_state->update_lrr); - if (intel_vrr_is_push_sent(crtc_state)) - evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state); - else - evade->vblank_start = intel_vrr_vmax_vblank_start(crtc_state); + evade->vblank_start = vrr_vblank_start(crtc_state); vblank_delay = intel_vrr_vblank_delay(crtc_state); } else { From patchwork Wed Apr 16 06:27:35 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 14053233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 761DEC369C9 for ; Wed, 16 Apr 2025 06:29:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DD5EC10E83B; Wed, 16 Apr 2025 06:29:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="EmeIGZFb"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 607BC10E83A for ; Wed, 16 Apr 2025 06:29:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744784993; x=1776320993; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=cdle4LkhKj4XV9Oj8cmzqk1kyrn/v5Y1rz4sM1dDjgw=; b=EmeIGZFbo9xF/+CY94NPpqdrBT2slNWRERyYgmn2725QCSrSOUGaFFQt EFyQCRBXIpS2PXcvCQHrNKWoXp3NVllL0O4BU35EKN+jShKC383XD7V7H yNekoVBcjj0+awR6tRgyWVeYwccdk8yu/uEcUfTSRTT0iZ+gov1Yf19dR NYiSOnImo6Z7Ry6OUmc4F6Atytb5fRGyY48JN443joSxdEmgDak7hxBCZ Jo/yJmvoXk/sbm3RXvVFBnXqEYypeYJDkeskORGMOCTAD48CvZTWqQIuz uFKEBwAfUZeb6O2kunTfGKur3ajypc/3uYKpZu5PmGanieChQoAu7Zz9O g==; X-CSE-ConnectionGUID: rtd+IOAxTdaWqS7ax7B6uw== X-CSE-MsgGUID: /9uoAdlBTAOUnQ3FLR7Zlw== X-IronPort-AV: E=McAfee;i="6700,10204,11404"; a="71710253" X-IronPort-AV: E=Sophos;i="6.15,215,1739865600"; d="scan'208";a="71710253" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 23:29:53 -0700 X-CSE-ConnectionGUID: Jf9VOJwoRX6PapKvLsHx0g== X-CSE-MsgGUID: T9lwHUHNS86uHmMLhJKEMw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,215,1739865600"; d="scan'208";a="130880207" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa007.jf.intel.com with ESMTP; 15 Apr 2025 23:29:52 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Subject: [PATCH v1 6/8] drm/i915/vrr: Implement vblank evasion with DC balancing Date: Wed, 16 Apr 2025 11:57:35 +0530 Message-ID: <20250416062737.1766703-7-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> References: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add vblank evasion logic when vrr is already enabled along with dc balance is computed. Signed-off-by: Ville Syrjälä --- .../drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_dsb.c | 31 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_vblank.c | 26 ++++++++++++++-- 3 files changed, 54 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 94468a9d2e0d..0e06c71e9086 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1303,7 +1303,7 @@ struct intel_crtc_state { /* Variable Refresh Rate state */ struct { - bool enable, in_range; + bool enable, in_range, dc_balance; u8 pipeline_full; u16 flipline, vmin, vmax, guardband; u32 vsync_end, vsync_start; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 72fe390c5af2..ed27cbff44fc 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -577,7 +577,36 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state, if (crtc_state->has_psr) intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0); - if (pre_commit_is_vrr_active(state, crtc)) { + if (pre_commit_is_vrr_active(state, crtc) && crtc_state->vrr.dc_balance) { + int vblank_delay = intel_vrr_vblank_delay(crtc_state); + int vmin_vblank_start, vmax_vblank_start; + + vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state); + + if (vmin_vblank_start >= 0) { + end = vmin_vblank_start; + start = end - vblank_delay - latency; + intel_dsb_wait_scanline_out(state, dsb, start, end); + } + + vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state); + + if (vmax_vblank_start >= 0) { + end = vmax_vblank_start; + start = end - vblank_delay - latency; + intel_dsb_wait_scanline_out(state, dsb, start, end); + } + + vmin_vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state); + end = vmin_vblank_start; + start = end - vblank_delay - latency; + intel_dsb_wait_scanline_out(state, dsb, start, end); + + vmax_vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state); + end = vmax_vblank_start; + start = end - vblank_delay - latency; + intel_dsb_wait_scanline_out(state, dsb, start, end); + } else if (pre_commit_is_vrr_active(state, crtc)) { int vblank_delay = intel_vrr_vblank_delay(crtc_state); end = intel_vrr_vmin_vblank_start(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 680013f00fc0..9b63e4217881 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -644,10 +644,30 @@ intel_pre_commit_crtc_state(struct intel_atomic_state *state, static int vrr_vblank_start(const struct intel_crtc_state *crtc_state) { - if (intel_vrr_is_push_sent(crtc_state)) - return intel_vrr_vmin_vblank_start(crtc_state); + bool is_push_sent = intel_vrr_is_push_sent(crtc_state); + int vblank_start; + + if (!crtc_state->vrr.dc_balance) { + if (is_push_sent) + return intel_vrr_vmin_vblank_start(crtc_state); + else + return intel_vrr_vmax_vblank_start(crtc_state); + } + + if (is_push_sent) + vblank_start = intel_vrr_dcb_vmin_vblank_start_next(crtc_state); else - return intel_vrr_vmax_vblank_start(crtc_state); + vblank_start = intel_vrr_dcb_vmax_vblank_start_next(crtc_state); + + if (vblank_start >= 0) + return vblank_start; + + if (is_push_sent) + vblank_start = intel_vrr_dcb_vmin_vblank_start_final(crtc_state); + else + vblank_start = intel_vrr_dcb_vmax_vblank_start_final(crtc_state); + + return vblank_start; } void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, From patchwork Wed Apr 16 06:27:36 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 14053234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37955C369C7 for ; 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X-CSE-ConnectionGUID: 5vs5KlSvQhOmG+/VU9BrCw== X-CSE-MsgGUID: ETZYX4BVTZe+QhZlqyoENg== X-IronPort-AV: E=McAfee;i="6700,10204,11404"; a="71710255" X-IronPort-AV: E=Sophos;i="6.15,215,1739865600"; d="scan'208";a="71710255" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2025 23:29:54 -0700 X-CSE-ConnectionGUID: zpAZi5pSSqyv//HyrQ0qnw== X-CSE-MsgGUID: fuqfBqLYTXKi07zQu0fiuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,215,1739865600"; d="scan'208";a="130880214" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa007.jf.intel.com with ESMTP; 15 Apr 2025 23:29:53 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Subject: [PATCH v1 7/8] drm/i915/dsb: Add pipedmc dc balance enable/disable Date: Wed, 16 Apr 2025 11:57:36 +0530 Message-ID: <20250416062737.1766703-8-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> References: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add function to control DC balance enable/disable bit via DSB. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dmc.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/display/intel_dmc.h | 5 +++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 98f80a6c63e8..17835b297f6d 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -30,6 +30,7 @@ #include "intel_de.h" #include "intel_display_rpm.h" #include "intel_display_power_well.h" +#include "intel_display_types.h" #include "intel_dmc.h" #include "intel_dmc_regs.h" #include "intel_step.h" @@ -1362,3 +1363,18 @@ void intel_dmc_debugfs_register(struct intel_display *display) debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, display, &intel_dmc_debugfs_status_fops); } + +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(crtc); + + intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(crtc->pipe), + PIPEDMC_ADAPTIVE_DCB_ENABLE); +} + +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc) +{ + struct intel_display *display = to_intel_display(crtc); + + intel_de_write_dsb(display, dsb, PIPEDMC_DCB_CTL(crtc->pipe), 0); +} diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h index c78426eb4cd5..74dcd142f5b1 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.h +++ b/drivers/gpu/drm/i915/display/intel_dmc.h @@ -10,8 +10,10 @@ enum pipe; struct drm_printer; +struct intel_crtc; struct intel_display; struct intel_dmc_snapshot; +struct intel_dsb; void intel_dmc_init(struct intel_display *display); void intel_dmc_load_program(struct intel_display *display); @@ -30,4 +32,7 @@ void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool star void assert_dmc_loaded(struct intel_display *display); +void intel_pipedmc_dcb_enable(struct intel_dsb *dsb, struct intel_crtc *crtc); +void intel_pipedmc_dcb_disable(struct intel_dsb *dsb, struct intel_crtc *crtc); + #endif /* __INTEL_DMC_H__ */ From patchwork Wed Apr 16 06:27:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 14053235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A973BC369BD for ; Wed, 16 Apr 2025 06:29:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 39F9810E83E; Wed, 16 Apr 2025 06:29:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bEkDxGKE"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7A19E10E83E for ; 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15 Apr 2025 23:29:55 -0700 X-CSE-ConnectionGUID: 3q4+NyLwSiuDdCS/AEJNiQ== X-CSE-MsgGUID: unFwNh9pTg6fQj9tLJdtbQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,215,1739865600"; d="scan'208";a="130880218" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa007.jf.intel.com with ESMTP; 15 Apr 2025 23:29:54 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org Subject: [PATCH v1 8/8] drm/i915/vrr: Pause DC balancing for DSB commits Date: Wed, 16 Apr 2025 11:57:37 +0530 Message-ID: <20250416062737.1766703-9-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> References: <20250416062737.1766703-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Pause the DMC DC balancing for the remainder of the commit so that vmin/vmax won't change after we've baked them into the DSB vblank evasion commands. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 13 ++++++ drivers/gpu/drm/i915/display/intel_vrr.c | 43 +++++++++++++++----- 2 files changed, 45 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index db524d01e574..7373c11e6e8d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7195,6 +7195,17 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, } if (new_crtc_state->use_dsb) { + /* + * Pause the DMC DC balancing for the remainder of the + * commit so that vmin/vmax won't change after we've baked + * them into the DSB vblank evasion commands. + * + * FIXME maybe need a small delay here to make sure DMC has + * finished updating the values? Or we need a better DMC<->driver + * protocol that gives is real guarantees about that... + */ + intel_pipedmc_dcb_disable(NULL, crtc); + if (intel_crtc_needs_color_update(new_crtc_state)) intel_color_commit_noarm(new_crtc_state->dsb_commit, new_crtc_state); @@ -7231,6 +7242,8 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); intel_dsb_wait_vblank_delay(state, new_crtc_state->dsb_commit); intel_vrr_check_push_sent(new_crtc_state->dsb_commit, new_crtc_state); + if (new_crtc_state->vrr.dc_balance) + intel_pipedmc_dcb_enable(new_crtc_state->dsb_commit, crtc); intel_dsb_interrupt(new_crtc_state->dsb_commit); } } diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 03405c274b8c..18c38afb9108 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -9,6 +9,7 @@ #include "i915_reg.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_dmc.h" #include "intel_dp.h" #include "intel_vrr.h" #include "intel_vrr_regs.h" @@ -576,7 +577,9 @@ bool intel_vrr_always_use_vrr_tg(struct intel_display *display) void intel_vrr_enable(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 ctl; if (!crtc_state->vrr.enable) return; @@ -587,33 +590,51 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) crtc_state->vrr.vmax - 1); intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), crtc_state->vrr.flipline - 1); + if (!intel_vrr_always_use_vrr_tg(display)) + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN); intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN); - if (!intel_vrr_always_use_vrr_tg(display)) { - if (crtc_state->cmrr.enable) { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | - trans_vrr_ctl(crtc_state)); - } else { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); - } + ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state); + if (crtc_state->cmrr.enable) + ctl |= VRR_CTL_CMRR_ENABLE; + if (crtc_state->vrr.dc_balance) + ctl |= VRR_CTL_DCB_ADJ_ENABLE; + + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl); + + if (crtc_state->vrr.dc_balance) { + /* FIXME reset counters? */ + intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), + ADAPTIVE_SYNC_COUNTER_EN); + /* FIMXE configure pipedmc DC balance parameters somewhere */ + intel_pipedmc_dcb_enable(NULL, crtc); } } void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) { struct intel_display *display = to_intel_display(old_crtc_state); + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; + u32 ctl; if (!old_crtc_state->vrr.enable) return; + if (old_crtc_state->vrr.dc_balance) { + intel_pipedmc_dcb_disable(NULL, crtc); + intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0); + } + + ctl = trans_vrr_ctl(old_crtc_state); + if (intel_vrr_always_use_vrr_tg(display)) + ctl |= VRR_CTL_VRR_ENABLE; + + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl); + if (!intel_vrr_always_use_vrr_tg(display)) { - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), - trans_vrr_ctl(old_crtc_state)); intel_de_wait_for_clear(display, TRANS_VRR_STATUS(display, cpu_transcoder), VRR_STATUS_VRR_EN_LIVE, 1000);