From patchwork Thu Apr 17 00:35:09 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 14054812 Received: from mail-m49225.qiye.163.com (mail-m49225.qiye.163.com [45.254.49.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6099A42A97 for ; Thu, 17 Apr 2025 02:57:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.225 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744858675; cv=none; b=FBHOcuTDFJko+JJMLlTTiNoT7Gri+ilRJq1TTli0YOAZe/pH4GRQ50lQ4QhdFANmdJ5iexUgrdLn+h8nd2nZDbRbew09kJAEncEHjA8KbAv25U5oBJlPKqnp3uKQIs3WkE7WNNITSV3ESIHW/0mqzgPuEmTsY+GbLfrRGbFyaoI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744858675; c=relaxed/simple; bh=bAr+kjHhgBzynygLxrZ/spJhCuPBJs3/xuEJy5wLyH8=; h=From:To:Cc:Subject:Date:Message-Id; b=FbTA7Ir/nNdruTmAxer+iquXqHO7G0B0Z9lnHf+Bv4HSzFX8z6KYR/aq0MNbz0+e2PfmK4YGMr7L8wN5SK/r0amuIweWxqbBMMu/zVcNRkLQGtvJjjq5ub8NSnH3LYhrugT1cJe8QYOK68NngGYX4EmxkvFKgT7jnBXIVKNuD/8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=ZeduLzrj; arc=none smtp.client-ip=45.254.49.225 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="ZeduLzrj" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 1224c9fc8; Thu, 17 Apr 2025 08:35:20 +0800 (GMT+08:00) From: Shawn Lin To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: Niklas Cassel , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Shawn Lin Subject: [PATCH v4 1/3] PCI: dw-rockchip: Remove PCIE_L0S_ENTRY check from rockchip_pcie_link_up() Date: Thu, 17 Apr 2025 08:35:09 +0800 Message-Id: <1744850111-236269-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 2.7.4 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQh9DGlYfGk5LGUxLSxgdShpWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a96412bf0db09cckunm1224c9fc8 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Nxw6PRw6KTJCChJMTlE5SRwQ PjxPCR9VSlVKTE9PQ05LSklKTE5PVTMWGhIXVQgTGgwVVRcSFTsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUlJQk43Bg++ DKIM-Signature: a=rsa-sha256; b=ZeduLzrjIPy5pH1Ewgvw5Tf5y1+XXufBjpE3azg6NjeweB+zZdorFsSaQXMoP4TE0fFiZfdOv7f2TzwXTHjlu+BG0ZactQTV4XlAdgYiZqqtetJQaIyfiKY4lzKaR2XxZSlyxeswu8LZLWSr0bBh/tJq2P8l4ZWO6i6qQCB1fNY=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=fq/Bq902UqO4acjVfAr3JCalQ1/clSsH0CNvIUMs4hw=; h=date:mime-version:subject:message-id:from; Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Two mistakes here: 1. 0x11 is L0 not L0S, so the naming is wrong from the very beginning. 2. It's totally broken if enabling ASPM as rockchip_pcie_link_up() treat other states, for instance, L0S or L1 as link down which is obviously wrong. Remove the check. Fixes: 0e898eb8df4e ("PCI: rockchip-dwc: Add Rockchip RK356X host controller driver") Signed-off-by: Shawn Lin Reviewed-by: Niklas Cassel --- Changes in v4: - add Niklas's review tag Changes in v3: None Changes in v2: - add Fixes tag drivers/pci/controller/dwc/pcie-dw-rockchip.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index c624b7e..21dc99c 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -44,7 +44,6 @@ #define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP) #define PCIE_RDLH_LINK_UP_CHGED BIT(1) #define PCIE_LINK_REQ_RST_NOT_INT BIT(2) -#define PCIE_L0S_ENTRY 0x11 #define PCIE_CLIENT_GENERAL_CONTROL 0x0 #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8 #define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c @@ -177,8 +176,7 @@ static int rockchip_pcie_link_up(struct dw_pcie *pci) struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); u32 val = rockchip_pcie_get_ltssm(rockchip); - if ((val & PCIE_LINKUP) == PCIE_LINKUP && - (val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY) + if ((val & PCIE_LINKUP) == PCIE_LINKUP) return 1; return 0; From patchwork Thu Apr 17 00:35:10 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 14054747 Received: from mail-m49239.qiye.163.com (mail-m49239.qiye.163.com [45.254.49.239]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71907747F for ; Thu, 17 Apr 2025 00:50:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.239 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744851052; cv=none; b=Io3htySxjXBbSCE6VKQkOqH1GQ5UxapJvyrKIlo5nPhdkLJ8lmVnx38ggipPl7p1ldautZasxJsHwVHJ1EmnhFLccUZmRw2Lg9kw2t6irdIGJ7K/i8oHbtLzbWPYgV97jx+ksp5MEtOVL0lqk6eXDCT0WdCA3FmCIyOac6Xu8nE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744851052; c=relaxed/simple; bh=/LIhYUtWCc/WbPgemz7WMG4qL/YHS6J7dOb5PnZq1e8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=s/iOGJMj4HKsaBtkABn9+cAT9hApgF1ijd4VSft+8FB5WyNo9Xld9GqtlkAqehhObFWYN8bwk3uZA1buzx1DmxzkgwsCgT0GynuKezWnvuV+Kw3YCTyzxnXSIzyc8n5C+YIFL8sjFG67e9G2s9qwQkBU+4UWQn96j2QZGsy/S/I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=Ll+f3hVi; arc=none smtp.client-ip=45.254.49.239 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="Ll+f3hVi" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 1224c9fcc; Thu, 17 Apr 2025 08:35:22 +0800 (GMT+08:00) From: Shawn Lin To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: Niklas Cassel , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Shawn Lin Subject: [PATCH v4 2/3] PCI: dw-rockchip: Enable L0S capability Date: Thu, 17 Apr 2025 08:35:10 +0800 Message-Id: <1744850111-236269-2-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1744850111-236269-1-git-send-email-shawn.lin@rock-chips.com> References: <1744850111-236269-1-git-send-email-shawn.lin@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGUoYH1YdGkJNT0NDSUJDHU9WFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a96412bf76d09cckunm1224c9fcc X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Mjo6Fjo6IjJPQxIsN1EaSRwU Mk4wFDNVSlVKTE9PQ05LSklITUtLVTMWGhIXVQgTGgwVVRcSFTsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUhPTkk3Bg++ DKIM-Signature: a=rsa-sha256; b=Ll+f3hVibvz98qjZUuX4AqAybXXMLdFBMW0bQ6td5t6TEeCzB1o7vSTxcekXYN16M1aC8Q8z28jWsZrQdNFVmyURC817M6PULpJk9MRrPOX9YNC1J4LkIwRBOTyFxtj2UMelxxP7B4tpVZwvXuIbNsACp9BvRQoMOFBfeH/wL/E=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=3zV4zLHBFMBDkTaI0ymuEzaxulPPeYl/7men0nXYlkA=; h=date:mime-version:subject:message-id:from; Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: L0S capability isn't enabled on all SoCs by default, so enabling it in order to make ASPM L0S work on Rockchip platforms. We have been testing it for quite a long time and found the default FTS number provided by DWC core doesn't work stable and make LTSSM switch between L0S and Recovery, leading to long exit latency, even fail to link sometimes. So override it to the max 255 which seems work fine under test for both PHYs used by Rockchip platforms. Signed-off-by: Shawn Lin Reviewed-by: Niklas Cassel --- Changes in v4: - Add Niklas's review tag Changes in v3: - Add rockchip_pcie_enable_l0s() and called from .init() Changes in v2: - Move n_fts to probe function - rewrite the commit message drivers/pci/controller/dwc/pcie-dw-rockchip.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 21dc99c..e4519c0 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -182,6 +182,21 @@ static int rockchip_pcie_link_up(struct dw_pcie *pci) return 0; } +static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) +{ + u32 cap, lnkcap; + + /* Enable L0S capability for all SoCs */ + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + if (cap) { + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + lnkcap |= PCI_EXP_LNKCAP_ASPM_L0S; + dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); + dw_pcie_dbi_ro_wr_dis(pci); + } +} + static int rockchip_pcie_start_link(struct dw_pcie *pci) { struct rockchip_pcie *rockchip = to_rockchip_pcie(pci); @@ -231,6 +246,8 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler, rockchip); + rockchip_pcie_enable_l0s(pci); + return 0; } @@ -271,6 +288,8 @@ static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep) struct dw_pcie *pci = to_dw_pcie_from_ep(ep); enum pci_barno bar; + rockchip_pcie_enable_l0s(pci); + for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) dw_pcie_ep_reset_bar(pci, bar); }; @@ -599,6 +618,10 @@ static int rockchip_pcie_probe(struct platform_device *pdev) rockchip->pci.ops = &dw_pcie_ops; rockchip->data = data; + /* Default N_FTS value (210) is broken, override it to 255 */ + rockchip->pci.n_fts[0] = 255; /* Gen1 */ + rockchip->pci.n_fts[1] = 255; /* Gen2+ */ + ret = rockchip_pcie_resource_get(pdev, rockchip); if (ret) return ret; From patchwork Thu Apr 17 00:35:11 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 14054964 Received: from mail-m19731105.qiye.163.com (mail-m19731105.qiye.163.com [220.197.31.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 843A61A2554 for ; Thu, 17 Apr 2025 06:18:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.105 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744870701; cv=none; b=Ki0NpVWq9j9K8sOAeWQqZREPCajmCpKdgdbMxNZVyCZSdDw17Yx9UATRVvyKBHl4x5ot1uPbPxrAvC8fXVd3l6cX68CrHKQVnPYnVs9NtEkxG/k9RY5W7uKnTHYgWc+Vf+faFQVtMrDUMM9VEmZbZgWSUiFocPShNpvVJOnJkrQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744870701; c=relaxed/simple; bh=illQQOeOEVGTjqjIqlrysskfdCsy8ZchpRLwgyjITaA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=YfN8gh4jUm14KJulUW1dAd511hYJ0rZR720LUUxH/vPT6++/5v4jLxKTAkGjuGWxYRn1H4XnlMlwi6hgKdLcADAXr4MfMH/a7BSg5o8lovMaL30VEOzdfMZK1fi2P48hsbSVo5jCm29RM/Pi9NfPC3t3FJOGb12j+LfTr+Vj5Eg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=OXDAedLj; arc=none smtp.client-ip=220.197.31.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="OXDAedLj" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 1224c9fd2; Thu, 17 Apr 2025 08:35:24 +0800 (GMT+08:00) From: Shawn Lin To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= Cc: Niklas Cassel , linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Shawn Lin Subject: [PATCH v4 3/3] PCI: dw-rockchip: Move rockchip_pcie_ep_hide_broken_ats_cap_rk3588() to .init() Date: Thu, 17 Apr 2025 08:35:11 +0800 Message-Id: <1744850111-236269-3-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1744850111-236269-1-git-send-email-shawn.lin@rock-chips.com> References: <1744850111-236269-1-git-send-email-shawn.lin@rock-chips.com> X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQh5OQlZCTRpKSE9NSUkfSRhWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ X-HM-Tid: 0a96412bfef009cckunm1224c9fd2 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Nio6MBw6NzJNEhILCUoNSRI6 Gg8aCQ5VSlVKTE9PQ05LSklOT0tIVTMWGhIXVQgTGgwVVRcSFTsJFBgQVhgTEgsIVRgUFkVZV1kS C1lBWU5DVUlJVUxVSkpPWVdZCAFZQUhLS003Bg++ DKIM-Signature: a=rsa-sha256; b=OXDAedLjWKEbZeQ+UyBkCJ8RP4tRq83/0lDfSrt756kpoj+DYKaaLzY9hYWyjFz8YhbG+Uz+I5tvVCqUPB7Yt4YQie8vvX9PcjHG3ePj+Avo+FmL7QI8U+37H9OkxBibyzEZI3bE0pVRNWlZQkQnE9syOMQCSd+K/hrBkWIuTGA=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=5zSHlWHLiEmdxc+sCW6tUdXwMlspj2a4pKO9Z8NdMAk=; h=date:mime-version:subject:message-id:from; Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: There is no reason to call rockchip_pcie_ep_hide_broken_ats_cap_rk3588() from the pre_init() callback, instead of the normal init() callback. Thus, move the rockchip_pcie_ep_hide_broken_ats_cap_rk3588() call from the pre_init() callback to the init() callback, as: 1) init() will still be called before link training is enabled, so the quirk will still be applied before the host has can see our device. 2) This allows us to remove the pre_init() callback, as it is now unused. 3) It is a more robust design, as the init() callback is called by dw_pcie_ep_init_registers(), which will always be called after a core reset. The pre_init() callback is only called once, at probe time. No functional changes. Suggested-by: Niklas Cassel Signed-off-by: Shawn Lin Reviewed-by: Niklas Cassel --- Changes in v4: - rewrite commit message Changes in v3: None Changes in v2: None drivers/pci/controller/dwc/pcie-dw-rockchip.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index e4519c0..7790a9f 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -278,17 +278,13 @@ static void rockchip_pcie_ep_hide_broken_ats_cap_rk3588(struct dw_pcie_ep *ep) dev_err(dev, "failed to hide ATS capability\n"); } -static void rockchip_pcie_ep_pre_init(struct dw_pcie_ep *ep) -{ - rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep); -} - static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); enum pci_barno bar; rockchip_pcie_enable_l0s(pci); + rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep); for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) dw_pcie_ep_reset_bar(pci, bar); @@ -359,7 +355,6 @@ rockchip_pcie_get_features(struct dw_pcie_ep *ep) static const struct dw_pcie_ep_ops rockchip_pcie_ep_ops = { .init = rockchip_pcie_ep_init, - .pre_init = rockchip_pcie_ep_pre_init, .raise_irq = rockchip_pcie_raise_irq, .get_features = rockchip_pcie_get_features, };