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Update the qcom,pcie-common.yaml to include the phy, phy-names, and wake-gpios properties in the root port node. There is already reset-gpios defined for PERST# in pci-bus-common.yaml, start using that property instead of perst-gpio. For backward compatibility, do not remove any existing properties in the bridge node. [1] https://lore.kernel.org/linux-pci/20241211192014.GA3302752@bhelgaas/ Signed-off-by: Krishna Chaitanya Chundru --- .../devicetree/bindings/pci/qcom,pcie-common.yaml | 36 ++++++++++++++++++++-- .../devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 16 +++++++--- 2 files changed, 46 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 0480c58f7d998adbac4c6de20cdaec945b3bab21..e5f60faa18ad68a29900a66fbfcba3d4f8e88e7b 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -51,10 +51,18 @@ properties: phys: maxItems: 1 + deprecated: true + description: + This property is deprecated, instead of referencing this property from + the controller node, use the property from the PCIe root port node. phy-names: items: - const: pciephy + deprecated: true + description: + Phandle to the register map node. This property is deprecated, and not + required to add in the root port also, as the root port has only one phy. power-domains: maxItems: 1 @@ -71,12 +79,18 @@ properties: maxItems: 12 perst-gpios: - description: GPIO controlled connection to PERST# signal + description: GPIO controlled connection to PERST# signal. This property is + deprecated, instead of referencing this property from the controller node, + use the reset-gpios property from the root port node. maxItems: 1 + deprecated: true wake-gpios: - description: GPIO controlled connection to WAKE# signal + description: GPIO controlled connection to WAKE# signal. This property is + deprecated, instead of referencing this property from the controller node, + use the property from the PCIe root port node. maxItems: 1 + deprecated: true vddpe-3v3-supply: description: PCIe endpoint power supply @@ -85,6 +99,24 @@ properties: opp-table: type: object +patternProperties: + "^pcie@": + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + phys: + maxItems: 1 + + wake-gpios: + description: GPIO controlled connection to WAKE# signal + maxItems: 1 + + unevaluatedProperties: false + required: - reg - reg-names diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml index 76cb9fbfd476fb0412217c68bd8db44a51c7d236..eb70cc6b6618af43fb03e124db20e2ade26a95ae 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml @@ -162,9 +162,6 @@ examples: iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, <0x100 &apps_smmu 0x1c81 0x1>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>; @@ -173,7 +170,18 @@ examples: resets = <&gcc GCC_PCIE_1_BCR>; reset-names = "pci"; - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&pp3300_ssd>; + pcie1_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + phys = <&pcie1_phy>; + + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + }; }; }; From patchwork Sat Apr 19 05:19:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 14057777 X-Patchwork-Delegate: manivannanece23@gmail.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EF8715747D for ; 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Currently, qcom controllers only support single port, and all properties are present in the controller node itself. This is incorrect, as properties like phy, perst, wake, etc. can vary per port and should be present in the root port node. To maintain DT backwards compatibility, fallback to the legacy method of parsing the controller node if the port parsing fails. pci-bus-common.yaml uses reset-gpios property for representing PERST, use same property instead of perst-gpios. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 169 +++++++++++++++++++++++++++------ 1 file changed, 142 insertions(+), 27 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index dc98ae63362db0422384b1879a2b9a7dc564d091..e97e5076f5f77acbbdfb982af7acc69daf9bf307 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -262,6 +262,11 @@ struct qcom_pcie_cfg { bool no_l0s; }; +struct qcom_pcie_port { + struct list_head list; + struct gpio_desc *reset; + struct phy *phy; +}; struct qcom_pcie { struct dw_pcie *pci; void __iomem *parf; /* DT parf */ @@ -276,22 +281,35 @@ struct qcom_pcie { struct dentry *debugfs; bool suspended; bool use_pm_opp; + struct list_head ports; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) -static void qcom_ep_reset_assert(struct qcom_pcie *pcie) +static void qcom_perst_assert_deassert(struct qcom_pcie *pcie, bool assert) { - gpiod_set_value_cansleep(pcie->reset, 1); + struct qcom_pcie_port *port, *tmp; + int val = assert ? 1 : 0; + + if (list_empty(&pcie->ports)) + gpiod_set_value_cansleep(pcie->reset, val); + else + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + gpiod_set_value_cansleep(port->reset, val); + usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } +static void qcom_ep_reset_assert(struct qcom_pcie *pcie) +{ + qcom_perst_assert_deassert(pcie, true); +} + static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) { /* Ensure that PERST has been asserted for at least 100 ms */ msleep(100); - gpiod_set_value_cansleep(pcie->reset, 0); - usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); + qcom_perst_assert_deassert(pcie, false); } static int qcom_pcie_start_link(struct dw_pcie *pci) @@ -1229,6 +1247,59 @@ static int qcom_pcie_link_up(struct dw_pcie *pci) return !!(val & PCI_EXP_LNKSTA_DLLLA); } +static void qcom_pcie_phy_exit(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port, *tmp; + + if (list_empty(&pcie->ports)) + phy_exit(pcie->phy); + else + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + phy_exit(port->phy); +} + +static void qcom_pcie_phy_off(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port, *tmp; + + if (list_empty(&pcie->ports)) { + phy_power_off(pcie->phy); + } else { + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + phy_power_off(port->phy); + } +} + +static int qcom_pcie_phy_power_on(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port, *tmp; + int ret = 0; + + if (list_empty(&pcie->ports)) { + ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); + if (ret) + goto out; + + ret = phy_power_on(pcie->phy); + if (ret) + goto out; + } else { + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + ret = phy_set_mode_ext(port->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); + if (ret) + goto out; + + ret = phy_power_on(port->phy); + if (ret) { + qcom_pcie_phy_off(pcie); + goto out; + } + } + } +out: + return ret; +} + static int qcom_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -1241,11 +1312,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) if (ret) return ret; - ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); - if (ret) - goto err_deinit; - - ret = phy_power_on(pcie->phy); + ret = qcom_pcie_phy_power_on(pcie); if (ret) goto err_deinit; @@ -1268,7 +1335,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) err_assert_reset: qcom_ep_reset_assert(pcie); err_disable_phy: - phy_power_off(pcie->phy); + qcom_pcie_phy_off(pcie); err_deinit: pcie->cfg->ops->deinit(pcie); @@ -1281,7 +1348,7 @@ static void qcom_pcie_host_deinit(struct dw_pcie_rp *pp) struct qcom_pcie *pcie = to_qcom_pcie(pci); qcom_ep_reset_assert(pcie); - phy_power_off(pcie->phy); + qcom_pcie_phy_off(pcie); pcie->cfg->ops->deinit(pcie); } @@ -1579,11 +1646,41 @@ static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) return IRQ_HANDLED; } +static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node) +{ + struct device *dev = pcie->pci->dev; + struct qcom_pcie_port *port; + struct gpio_desc *reset; + struct phy *phy; + + reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node), + "reset", GPIOD_OUT_HIGH, "PERST#"); + if (IS_ERR(reset)) + return PTR_ERR(reset); + + phy = devm_of_phy_get(dev, node, NULL); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + port->reset = reset; + port->phy = phy; + INIT_LIST_HEAD(&port->list); + list_add_tail(&port->list, &pcie->ports); + + return 0; +} + static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; unsigned long max_freq = ULONG_MAX; + struct qcom_pcie_port *port, *tmp; struct device *dev = &pdev->dev; + struct device_node *of_port; struct dev_pm_opp *opp; struct qcom_pcie *pcie; struct dw_pcie_rp *pp; @@ -1611,6 +1708,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) if (ret < 0) goto err_pm_runtime_put; + INIT_LIST_HEAD(&pcie->ports); + pci->dev = dev; pci->ops = &dw_pcie_ops; pp = &pci->pp; @@ -1619,12 +1718,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) pcie->cfg = pcie_cfg; - pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); - if (IS_ERR(pcie->reset)) { - ret = PTR_ERR(pcie->reset); - goto err_pm_runtime_put; - } - pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); if (IS_ERR(pcie->parf)) { ret = PTR_ERR(pcie->parf); @@ -1647,12 +1740,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) } } - pcie->phy = devm_phy_optional_get(dev, "pciephy"); - if (IS_ERR(pcie->phy)) { - ret = PTR_ERR(pcie->phy); - goto err_pm_runtime_put; - } - /* OPP table is optional */ ret = devm_pm_opp_of_add_table(dev); if (ret && ret != -ENODEV) { @@ -1699,9 +1786,35 @@ static int qcom_pcie_probe(struct platform_device *pdev) pp->ops = &qcom_pcie_dw_ops; - ret = phy_init(pcie->phy); - if (ret) - goto err_pm_runtime_put; + for_each_available_child_of_node(dev->of_node, of_port) { + ret = qcom_pcie_parse_port(pcie, of_port); + of_node_put(of_port); + if (ret) + break; + } + + /* + * In the case of failure in parsing the port nodes, fallback to the + * legacy method of parsing the controller node. This is to maintain DT + * backwards compatibility. + */ + if (ret) { + pcie->phy = devm_phy_optional_get(dev, "pciephy"); + if (IS_ERR(pcie->phy)) { + ret = PTR_ERR(pcie->phy); + goto err_pm_runtime_put; + } + + pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); + if (IS_ERR(pcie->reset)) { + ret = PTR_ERR(pcie->reset); + goto err_pm_runtime_put; + } + + ret = phy_init(pcie->phy); + if (ret) + goto err_pm_runtime_put; + } platform_set_drvdata(pdev, pcie); @@ -1746,10 +1859,12 @@ static int qcom_pcie_probe(struct platform_device *pdev) err_host_deinit: dw_pcie_host_deinit(pp); err_phy_exit: - phy_exit(pcie->phy); + qcom_pcie_phy_exit(pcie); err_pm_runtime_put: pm_runtime_put(dev); pm_runtime_disable(dev); + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + list_del(&port->list); return ret; } From patchwork Sat Apr 19 05:19:26 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 14057778 X-Patchwork-Delegate: manivannanece23@gmail.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6C821917F4 for ; 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Fri, 18 Apr 2025 22:19:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHRbu7EqDkT1Nj/uU8mVqGS+zdhQm81Ykk2C//aenToa25p2Tc/dc5T7ALGhEC7c4FKDOyS6w== X-Received: by 2002:a05:6a20:c90e:b0:1f5:9098:e446 with SMTP id adf61e73a8af0-203cbc0573emr8333308637.2.1745039988817; Fri, 18 Apr 2025 22:19:48 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73dbfaac258sm2607932b3a.144.2025.04.18.22.19.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 22:19:48 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Sat, 19 Apr 2025 10:49:26 +0530 Subject: [PATCH v3 3/3] arm64: qcom: sc7280: Move phy, perst to root port node Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250419-perst-v3-3-1afec3c4ea62@oss.qualcomm.com> References: <20250419-perst-v3-0-1afec3c4ea62@oss.qualcomm.com> In-Reply-To: <20250419-perst-v3-0-1afec3c4ea62@oss.qualcomm.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1745039969; l=3429; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=3DnAtxNAZDqNQqcmKUvx3DsvQPY0Kl35D9B1JCC1B6M=; b=DkSLSP7iTAUMhyijELwXlNgBv5oqQeFeYWwepFB2dZoS6R8mMcJt/WlFR72Rni98O5mLUSOEt I91VDY8Pa5yA8+u/2AHDaN1UzlvOeEfsYAXRomY41Exvys59O681HAi X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Authority-Analysis: v=2.4 cv=IpEecK/g c=1 sm=1 tr=0 ts=68033276 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=qQkGquXN9PvF_GGjQ98A:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: YffXWs9T4MfBwWpa5XW8aQ5_7olicCoX X-Proofpoint-ORIG-GUID: YffXWs9T4MfBwWpa5XW8aQ5_7olicCoX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-19_01,2025-04-17_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 adultscore=0 clxscore=1015 bulkscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 impostorscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504190040 There are many places we agreed to move the wake and perst gpio's and phy etc to the pcie root port node instead of bridge node[1]. So move the phy, phy-names, wake-gpio's in the root port. There is already reset-gpio defined for PERST# in pci-bus-common.yaml, start using that property instead of perst-gpio. [1] https://lore.kernel.org/linux-pci/20241211192014.GA3302752@bhelgaas/ Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 5 ++++- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 5 ++++- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 5 ++++- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++---- 4 files changed, 14 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 7a36c90ad4ec8b52f30b22b1621404857d6ef336..3dd58986ad5da0f898537a51715bb5d0fecbe100 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -709,8 +709,11 @@ &mdss_edp_phy { status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 2ba4ea60cb14736c9cfbf9f4a9048f20a4c921f2..ff11d85d015bdab6a90bd8a0eb9113a339866953 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -472,10 +472,13 @@ &pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>; - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&pp3300_ssd>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pm8350c_pwm { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 7370aa0dbf0e3f9e7a3e38c3f00686e1d3dcbc9f..3209bb15dfec36299cabae07d34f3dc82db6de77 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -414,9 +414,12 @@ &lpass_va_macro { vdd-micb-supply = <&vreg_bob>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pcie1 { status = "okay"; - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&nvme_3v3_regulator>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0f2caf36910b65c398c9e03800a8ce0a8a1f8fc7..376fabf3b4eac34d75bb79ef902c9d83490c45f7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2271,9 +2271,6 @@ pcie1: pcie@1c08000 { power-domains = <&gcc GCC_PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>; @@ -2284,7 +2281,7 @@ pcie1: pcie@1c08000 { status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2292,6 +2289,7 @@ pcie@0 { #address-cells = <3>; #size-cells = <2>; ranges; + phys = <&pcie1_phy>; }; };