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Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 1 + arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index f54db6345b7af6f77bde496d4a07b857bf9d5f6e..ebfe2c5347be02ea730039e61401633fa49479d2 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -711,6 +711,7 @@ &mdss_edp_phy { &pcieport1 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; }; &pcie1 { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 60b3cf50ea1d61dd5e8b573b5f1c6faa1c291eee..d435db860625d52842bf8e92d6223f67343121db 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -477,6 +477,7 @@ &pcie1 { &pcieport1 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; }; &pm8350c_pwm { diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 19910670fc3a74628e6def6b8faf2fa17991d576..e107ae0d62460d0d0909c7351c17b0b15f99a235 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -416,6 +416,7 @@ &lpass_va_macro { &pcieport1 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; }; &pcie1 { From patchwork Sat Apr 19 05:43:04 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Chaitanya Chundru X-Patchwork-Id: 14057789 X-Patchwork-Delegate: manivannanece23@gmail.com Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB85B19066D for ; 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a=ed25519-sha256; t=1745041398; l=5149; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=l+iLQRs3Sd9q7CUv85IAG9PJ5au9ED/F26dF58ymUtk=; b=Y3KF+GIIZYUGLI6u3qqIz8HUKIe4N/LUFLwc4f/nbvf/ewo8/wiGDrihcavfWs4SaYd9VSleO s+isiQTAOLfDcGjNQPpie72yhaQFIUqCPiiKgGS72yxjAIgT6hoHMeH X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Authority-Analysis: v=2.4 cv=ZOrXmW7b c=1 sm=1 tr=0 ts=68033805 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=iljMX2kAvVRlE-iODa4A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: yjqVPhGL-Wxzg1C5s41HfEcdcTqmDpn0 X-Proofpoint-ORIG-GUID: yjqVPhGL-Wxzg1C5s41HfEcdcTqmDpn0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-19_02,2025-04-17_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 mlxlogscore=999 bulkscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 mlxscore=0 suspectscore=0 phishscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504190043 PCIe wake interrupt is needed for bringing back PCIe device state from D3cold to D0. Implement new functions, of_pci_setup_wake_irq() and of_pci_teardown_wake_irq(), to manage wake interrupts for PCI devices using the Device Tree. From the port bus driver call these functions to enable wake support for bridges. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/of.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 6 +++++ drivers/pci/pcie/portdrv.c | 12 +++++++++- 3 files changed, 77 insertions(+), 1 deletion(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index ab7a8252bf4137a17971c3eb8ab70ce78ca70969..13623797c88a03dfb9d9079518d87a5e1e68df38 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) "PCI: OF: " fmt #include +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include +#include #include "pci.h" #ifdef CONFIG_PCI @@ -966,3 +968,61 @@ u32 of_pci_get_slot_power_limit(struct device_node *node, return slot_power_limit_mw; } EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); + +/** + * of_pci_setup_wake_irq - Set up wake interrupt for PCI device + * @pdev: The PCI device structure + * + * This function sets up the wake interrupt for a PCI device by getting the + * corresponding GPIO pin from the device tree, and configuring it as a + * dedicated wake interrupt. + * + * Return: 0 if the wake gpio is not available or successfully parsed else + * errno otherwise. + */ +int of_pci_setup_wake_irq(struct pci_dev *pdev) +{ + struct gpio_desc *wake; + struct device_node *dn; + int ret, wake_irq; + + dn = pci_device_to_OF_node(pdev); + if (!dn) + return 0; + + wake = devm_fwnode_gpiod_get(&pdev->dev, of_fwnode_handle(dn), + "wake", GPIOD_IN, NULL); + if (IS_ERR(wake)) { + dev_warn(&pdev->dev, "Cannot get wake GPIO\n"); + return 0; + } + + wake_irq = gpiod_to_irq(wake); + device_init_wakeup(&pdev->dev, true); + + ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, wake_irq); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to set wake IRQ: %d\n", ret); + device_init_wakeup(&pdev->dev, false); + return ret; + } + irq_set_irq_type(wake_irq, IRQ_TYPE_EDGE_FALLING); + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_setup_wake_irq); + +/** + * of_pci_teardown_wake_irq - Teardown wake interrupt setup for PCI device + * + * @pdev: The PCI device structure + * + * This function tears down the wake interrupt setup for a PCI device, + * clearing the dedicated wake interrupt and disabling device wake-up. + */ +void of_pci_teardown_wake_irq(struct pci_dev *pdev) +{ + dev_pm_clear_wake_irq(&pdev->dev); + device_init_wakeup(&pdev->dev, false); +} +EXPORT_SYMBOL_GPL(of_pci_teardown_wake_irq); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index b81e99cd4b62a3022c8b07a09f212f6888674487..b2f65289f4156fa1851c2d2f20c4ca948f36258f 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -888,6 +888,9 @@ void pci_release_of_node(struct pci_dev *dev); void pci_set_bus_of_node(struct pci_bus *bus); void pci_release_bus_of_node(struct pci_bus *bus); +int of_pci_setup_wake_irq(struct pci_dev *pdev); +void of_pci_teardown_wake_irq(struct pci_dev *pdev); + int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); bool of_pci_supply_present(struct device_node *np); @@ -931,6 +934,9 @@ static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_br return 0; } +static int of_pci_setup_wake_irq(struct pci_dev *pdev) { return 0; } +static void of_pci_teardown_wake_irq(struct pci_dev *pdev) { } + static inline bool of_pci_supply_present(struct device_node *np) { return false; diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index e8318fd5f6ed537a1b236a3a0f054161d5710abd..33220ecf821c348d49782855eb5aa3f2fe5c335e 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -694,12 +694,18 @@ static int pcie_portdrv_probe(struct pci_dev *dev, (type != PCI_EXP_TYPE_RC_EC))) return -ENODEV; + status = of_pci_setup_wake_irq(dev); + if (status) + return status; + if (type == PCI_EXP_TYPE_RC_EC) pcie_link_rcec(dev); status = pcie_port_device_register(dev); - if (status) + if (status) { + of_pci_teardown_wake_irq(dev); return status; + } pci_save_state(dev); @@ -732,6 +738,8 @@ static void pcie_portdrv_remove(struct pci_dev *dev) pcie_port_device_remove(dev); + of_pci_teardown_wake_irq(dev); + pci_disable_device(dev); } @@ -744,6 +752,8 @@ static void pcie_portdrv_shutdown(struct pci_dev *dev) } pcie_port_device_remove(dev); + + of_pci_teardown_wake_irq(dev); } static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev,