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Mon, 25 Mar 2019 03:42:41 -0700 (PDT) From: Jerome Brunet To: Neil Armstrong Subject: [PATCH] clk: meson: g12a: fix gp0 and hifi ranges Date: Mon, 25 Mar 2019 11:42:30 +0100 Message-Id: <20190325104230.11245-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190325_034245_246663_90D48E53 X-CRM114-Status: GOOD ( 11.62 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+patchwork-linux-amlogic=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP While some SoC samples are able to lock with a PLL factor of 55, others samples can't. ATM, a minimum of 60 appears to work on all the samples I have tried, so lets use this value until we have a good reason to put something else. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Jerome Brunet Acked-by: Neil Armstrong --- drivers/clk/meson/g12a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 0e1ce8c03259..d3f53a9b97dc 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -151,7 +151,7 @@ static struct clk_regmap g12a_sys_pll = { }; static const struct pll_mult_range g12a_gp0_pll_mult_range = { - .min = 55, + .min = 60, .max = 255, };