From patchwork Thu Mar 28 15:04:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Woods, Brian" X-Patchwork-Id: 10875099 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C9F1F186E for ; Thu, 28 Mar 2019 15:07:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B373828565 for ; Thu, 28 Mar 2019 15:07:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A752E28AB8; Thu, 28 Mar 2019 15:07:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.0 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 37F6528565 for ; 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Thu, 28 Mar 2019 15:04:54 +0000 Received: from MWHPR12MB1597.namprd12.prod.outlook.com ([fe80::d8d0:f630:f358:d1a8]) by MWHPR12MB1597.namprd12.prod.outlook.com ([fe80::d8d0:f630:f358:d1a8%9]) with mapi id 15.20.1730.019; Thu, 28 Mar 2019 15:04:54 +0000 From: "Woods, Brian" To: "xen-devel@lists.xen.org" Thread-Topic: [PATCH v2 1/3] mwait-idle: add support for using halt Thread-Index: AQHU5XeZQOYGihi64UuNi/EebXFZig== Date: Thu, 28 Mar 2019 15:04:54 +0000 Message-ID: <20190328150426.7295-2-brian.woods@amd.com> References: <20190328150426.7295-1-brian.woods@amd.com> In-Reply-To: <20190328150426.7295-1-brian.woods@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN1PR12CA0048.namprd12.prod.outlook.com (2603:10b6:802:20::19) To MWHPR12MB1597.namprd12.prod.outlook.com (2603:10b6:301:10::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Brian.Woods@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.11.0 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: cd60cbcf-0962-4eb6-7e84-08d6b38ebbd0 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: qm75stcWmRZZ0O3MvV+oDunv7yE/I9eWQROZ+EdVp36uoaZTGgST3StU4v0OFdV09lVOFQDnj9FiIvhICkWSV1wk09YRy3eZlhsAUB9XxuUEBdDJFFHSduRAwKpbZ2Z9rIQbfejOuyHVi0h+ZxGpwErsJxNw09Lv5+mxBK4VAjSmTw4xXh5llSBUmJlPuoQX7Gq0eQbVSOx1FJsm++9lOKm/Yiz9Emwx+6znk5exdY08JTc+eqpov+9aTi1M+suKkDejhz5f1ih5g9ajjglVU2bN0MCNC9HFoRgjag4H1OEXhK52bDcRKwiiECejoqxBfr9rir8vgLw9MnZyjhvBodIOF0t9FWvlcVVYq43Sxg4pyBQu+fq7Tz1rF7E4xSgaYSOHgib07ZuvJ6PhrDG4EoTigK0qWipufvTQukXXKks= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: cd60cbcf-0962-4eb6-7e84-08d6b38ebbd0 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Mar 2019 15:04:54.1989 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1709 Subject: [Xen-devel] [PATCH v2 1/3] mwait-idle: add support for using halt X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , "Woods, Brian" , Jan Beulich , =?iso-8859-1?q?Roger_Pau_Monn=E9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Brian Woods Some AMD processors can use a mixture of mwait and halt for accessing various c-states. In preparation for adding support for AMD processors, update the mwait-idle driver to optionally use halt. Signed-off-by: Brian Woods --- xen/arch/x86/acpi/cpu_idle.c | 2 +- xen/arch/x86/cpu/mwait-idle.c | 19 +++++++++++++------ xen/include/asm-x86/cpuidle.h | 1 + 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c index 654de24f40..b45824d343 100644 --- a/xen/arch/x86/acpi/cpu_idle.c +++ b/xen/arch/x86/acpi/cpu_idle.c @@ -439,7 +439,7 @@ static void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx) mwait_idle_with_hints(cx->address, MWAIT_ECX_INTERRUPT_BREAK); } -static void acpi_idle_do_entry(struct acpi_processor_cx *cx) +void acpi_idle_do_entry(struct acpi_processor_cx *cx) { struct cpu_info *info = get_cpu_info(); diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index f89c52f256..b9c7f75882 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -103,6 +103,11 @@ static const struct cpuidle_state { #define CPUIDLE_FLAG_DISABLED 0x1 /* + * On certain AMD families that support mwait, only c1 can be reached by + * mwait and to reach c2, halt has to be used. + */ +#define CPUIDLE_FLAG_USE_HALT 0x2 +/* * Set this flag for states where the HW flushes the TLB for us * and so we don't need cross-calls to keep it consistent. * If this flag is set, SW flushes the TLB, so even if the @@ -784,7 +789,7 @@ static void mwait_idle(void) update_last_cx_stat(power, cx, before); if (cpu_is_haltable(cpu)) - mwait_idle_with_hints(eax, MWAIT_ECX_INTERRUPT_BREAK); + acpi_idle_do_entry(cx); after = cpuidle_get_tick(); @@ -1184,8 +1189,9 @@ static int mwait_idle_cpu_init(struct notifier_block *nfb, for (cstate = 0; cpuidle_state_table[cstate].target_residency; ++cstate) { unsigned int num_substates, hint, state; struct acpi_processor_cx *cx; + const unsigned int cflags = cpuidle_state_table[cstate].flags; - hint = flg2MWAIT(cpuidle_state_table[cstate].flags); + hint = flg2MWAIT(cflags); state = MWAIT_HINT2CSTATE(hint) + 1; if (state > max_cstate) { @@ -1196,13 +1202,13 @@ static int mwait_idle_cpu_init(struct notifier_block *nfb, /* Number of sub-states for this state in CPUID.MWAIT. */ num_substates = (mwait_substates >> (state * 4)) & MWAIT_SUBSTATE_MASK; + /* If NO sub-states for this state in CPUID, skip it. */ - if (num_substates == 0) + if (num_substates == 0 && !(cflags & CPUIDLE_FLAG_USE_HALT)) continue; /* if state marked as disabled, skip it */ - if (cpuidle_state_table[cstate].flags & - CPUIDLE_FLAG_DISABLED) { + if (cflags & CPUIDLE_FLAG_DISABLED) { printk(XENLOG_DEBUG PREFIX "state %s is disabled", cpuidle_state_table[cstate].name); continue; @@ -1221,7 +1227,8 @@ static int mwait_idle_cpu_init(struct notifier_block *nfb, cx = dev->states + dev->count; cx->type = state; cx->address = hint; - cx->entry_method = ACPI_CSTATE_EM_FFH; + cx->entry_method = cflags & CPUIDLE_FLAG_USE_HALT ? + ACPI_CSTATE_EM_HALT : ACPI_CSTATE_EM_FFH; cx->latency = cpuidle_state_table[cstate].exit_latency; cx->target_residency = cpuidle_state_table[cstate].target_residency; diff --git a/xen/include/asm-x86/cpuidle.h b/xen/include/asm-x86/cpuidle.h index 08da01803f..33c8cf1593 100644 --- a/xen/include/asm-x86/cpuidle.h +++ b/xen/include/asm-x86/cpuidle.h @@ -18,6 +18,7 @@ extern uint64_t (*cpuidle_get_tick)(void); int mwait_idle_init(struct notifier_block *); int cpuidle_init_cpu(unsigned int cpu); +void acpi_idle_do_entry(struct acpi_processor_cx *cx); void default_dead_idle(void); void acpi_dead_idle(void); void trace_exit_reason(u32 *irq_traced); From patchwork Thu Mar 28 15:04:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Woods, Brian" X-Patchwork-Id: 10875095 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E8A571390 for ; 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Thu, 28 Mar 2019 15:04:58 +0000 Received: from MWHPR12MB1597.namprd12.prod.outlook.com ([fe80::d8d0:f630:f358:d1a8]) by MWHPR12MB1597.namprd12.prod.outlook.com ([fe80::d8d0:f630:f358:d1a8%9]) with mapi id 15.20.1730.019; Thu, 28 Mar 2019 15:04:58 +0000 From: "Woods, Brian" To: "xen-devel@lists.xen.org" Thread-Topic: [PATCH v2 2/3] mwait-idle: add support for AMD processors Thread-Index: AQHU5XecjZm2W8agMECWgwx39HNo0w== Date: Thu, 28 Mar 2019 15:04:58 +0000 Message-ID: <20190328150426.7295-3-brian.woods@amd.com> References: <20190328150426.7295-1-brian.woods@amd.com> In-Reply-To: <20190328150426.7295-1-brian.woods@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN1PR12CA0048.namprd12.prod.outlook.com (2603:10b6:802:20::19) To MWHPR12MB1597.namprd12.prod.outlook.com (2603:10b6:301:10::10) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Brian.Woods@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.11.0 x-originating-ip: [165.204.78.1] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 464d6c5d-ba3c-4a44-0d45-08d6b38ebe5d x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: /bCA9RI+4h6BKRJrGr5Hm09PmbUiXbNZShwaDc6PBGlczlE4H1NEJXcqdIFyzTRmi9vboANncV3XStk8rXJ+6R2KIomy8rZo34zXRoGqT7zQ9dnZOb1UGAOcuWBFtcCkH5fQV0h1UL7vPvPcM2b4m9bABuOniZ/RWc6pn1M5m/9SN1tUWhZ99MT9dy2Bstr2z2PYHJ+pNpiwBgeSCYO9NziHzvkbA6ky/E5pPeTUkCYkKfIbb/ZtqGy/oN0BEsrmgdXx3TkBDLU3VaYrPTxX3/RjLKZ4BUjwy5Okr/9F4FjA9tY2eL3hcqLTXUenkS2zPeWeGwm2reB5iXjFuoy9Ar/RiIJUI8dEOONVqgPG+UZvvg9ePGYLqTDVGi74zw8UCNZcDsKWiiNqZYDJx20zpY/I3orv92Glyzf5tu0z2cc= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 464d6c5d-ba3c-4a44-0d45-08d6b38ebe5d X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Mar 2019 15:04:58.3734 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1454 Subject: [Xen-devel] [PATCH v2 2/3] mwait-idle: add support for AMD processors X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , "Woods, Brian" , Jan Beulich , =?iso-8859-1?q?Roger_Pau_Monn=E9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Brian Woods Newer AMD processors (F17h) have mwait support which is compatible with Intel. Add some checks to make sure vendor specific code is run correctly and some infrastructure to facilitate adding AMD processors. This is done so that Xen will not be reliant on dom0 passing the parsed ACPI tables back since Xen doesn't have an AML interpreter. This can be unreliable or broken in some cases. Signed-off-by: Brian Woods --- xen/arch/x86/cpu/mwait-idle.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index b9c7f75882..58629f1c29 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -964,6 +964,13 @@ static const struct x86_cpu_id intel_idle_ids[] __initconstrel = { {} }; +#define ACPU(family, model, cpu) \ + { X86_VENDOR_AMD, family, model, X86_FEATURE_ALWAYS, &idle_cpu_##cpu} + +static const struct x86_cpu_id amd_idle_ids[] __initconstrel = { + {} +}; + /* * ivt_idle_state_table_update(void) * @@ -1100,6 +1107,9 @@ static void __init sklh_idle_state_table_update(void) */ static void __init mwait_idle_state_table_update(void) { + if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) + return; + switch (boot_cpu_data.x86_model) { case 0x3e: /* IVT */ ivt_idle_state_table_update(); @@ -1117,7 +1127,16 @@ static void __init mwait_idle_state_table_update(void) static int __init mwait_idle_probe(void) { unsigned int eax, ebx, ecx; - const struct x86_cpu_id *id = x86_match_cpu(intel_idle_ids); + const struct x86_cpu_id *id = NULL; + + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_INTEL: + id = x86_match_cpu(intel_idle_ids); + break; + case X86_VENDOR_AMD: + id = x86_match_cpu(amd_idle_ids); + break; + } if (!id) { pr_debug(PREFIX "does not run on family %d model %d\n", From patchwork Thu Mar 28 15:05:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Woods, Brian" X-Patchwork-Id: 10875097 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DC2091390 for ; Thu, 28 Mar 2019 15:06:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C683828565 for ; Thu, 28 Mar 2019 15:06:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BA91628AB8; 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DIR:OUT; SFP:1101; SCL:1; SRVR:MWHPR12MB1454; H:MWHPR12MB1597.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: A0USXHlMYaNlv90L8MHsot54vphTrS8nUFXvsnn1rguNfb49AwaI6HSwnfWC7gUQhhlB/R+MXP5P7uE2HnHi642Q36DO/aXmNyYv3sH/umera3kZ6EHJJ44sOnvkot2dNXqkj/4kJUSueviEqaITfvHjrFaShg5ZSM9D/FY1omMNC14ooT8jftMUvuHV+0liAf+sfMf9QDSORb/0dxLd5ConH/taBP21kaPfuAZ3EYUOhq3Oyk4AB751hIn5PSvf3+bPf/lGi74jMQWshmKPd2vYYgYDBdwpNS72iQBzKhHPim+SlC5crTVoC1GtHJLoWD06qlSjU0rTXSqHHGJwB377Ws8cf7S/FVxi506/3XK+YhB5MrHOsXJS7rsRDp0deY1jgrXJFtl5X3nx+EsWq7tY/t1j1Knvf3LEBh5m9sk= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: cfb37d95-2974-4dd3-07ab-08d6b38ec034 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Mar 2019 15:05:01.5100 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1454 Subject: [Xen-devel] [PATCH v2 3/3] mwait-idle: add enablement for AMD Naples and Rome X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , "Woods, Brian" , Jan Beulich , =?iso-8859-1?q?Roger_Pau_Monn=E9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Brian Woods Add the needed data structures for enabling Naples (F17h M01h). Since Rome (F17h M31h) has the same c-state latencies and entry methods, the c-state information can be used for Rome as well. For both Naples and Rome, mwait is used for c1 (cc1) and halt is functionally the same as c2 (cc6). If c2 (cc6) is disabled in BIOS, then halt functions similar to c1 (cc1). Signed-off-by: Brian Woods --- xen/arch/x86/cpu/mwait-idle.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c index 58629f1c29..0d5d4caa4d 100644 --- a/xen/arch/x86/cpu/mwait-idle.c +++ b/xen/arch/x86/cpu/mwait-idle.c @@ -720,6 +720,22 @@ static const struct cpuidle_state dnv_cstates[] = { {} }; +static const struct cpuidle_state naples_cstates[] = { + { + .name = "CC1", + .flags = MWAIT2flg(0x00), + .exit_latency = 1, + .target_residency = 2, + }, + { + .name = "CC6", + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_USE_HALT, + .exit_latency = 400, + .target_residency = 1000, + }, + {} +}; + static void mwait_idle(void) { unsigned int cpu = smp_processor_id(); @@ -964,10 +980,16 @@ static const struct x86_cpu_id intel_idle_ids[] __initconstrel = { {} }; +static const struct idle_cpu idle_cpu_naples = { + .state_table = naples_cstates, +}; + #define ACPU(family, model, cpu) \ { X86_VENDOR_AMD, family, model, X86_FEATURE_ALWAYS, &idle_cpu_##cpu} static const struct x86_cpu_id amd_idle_ids[] __initconstrel = { + ACPU(0x17, 0x01, naples), + ACPU(0x17, 0x31, naples), /* Rome shares the same c-state config */ {} };