From patchwork Fri Mar 29 22:10:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877809 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B04C17E0 for ; Fri, 29 Mar 2019 22:11:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 56AEE28E8F for ; Fri, 29 Mar 2019 22:11:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4A989292AE; Fri, 29 Mar 2019 22:11:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EDF6E28E8F for ; Fri, 29 Mar 2019 22:11:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DA20E6E553; Fri, 29 Mar 2019 22:11:31 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id CE8DD6E554 for ; Fri, 29 Mar 2019 22:11:28 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="136017276" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga008.fm.intel.com with ESMTP; 29 Mar 2019 15:11:26 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0R017079; Fri, 29 Mar 2019 22:11:24 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:10:49 +0000 Message-Id: <20190329221118.17308-2-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 01/30] drm/i915/guc: Don't allow GuC submission on pre-Gen11 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sujaritha Sundaresan MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Due to the GuC interface changes, new firmware releases will stop support GuC submission mode for pre-Gen11 platforms. Sanitize the enable_guc option so that only HuC authentication would be possible. Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Rodrigo Vivi Cc: Daniele Ceraolo Spurio Cc: John Spotswood Cc: Vinay Belgaumkar Cc: Tony Ye Cc: Anusha Srivatsa Cc: Jeff Mcgee Cc: Antonio Argenziano Cc: Sujaritha Sundaresan --- drivers/gpu/drm/i915/intel_uc.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 2d360d53757f..61d2a2910ef1 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -63,7 +63,9 @@ static int __get_platform_enable_guc(struct drm_i915_private *i915) if (intel_uc_fw_is_selected(huc_fw)) enable_guc |= ENABLE_GUC_LOAD_HUC; - /* Any platform specific fine-tuning can be done here */ + /* Don't allow GuC submission on pre-Gen11 */ + if (INTEL_GEN(i915) < 11) + enable_guc &= ~ENABLE_GUC_SUBMISSION; return enable_guc; } @@ -116,6 +118,13 @@ static void sanitize_options_early(struct drm_i915_private *i915) yesno(intel_uc_is_using_guc_submission(i915)), yesno(intel_uc_is_using_huc(i915))); + /* Verify GuC submission support */ + if (intel_uc_is_using_guc_submission(i915) && INTEL_GEN(i915) < 11) { + DRM_WARN("Incompatible option detected: %s=%d, %s!\n", + "enable_guc", i915_modparams.enable_guc, + "submission not supported"); + } + /* Verify GuC firmware availability */ if (intel_uc_is_using_guc(i915) && !intel_uc_fw_is_selected(guc_fw)) { DRM_WARN("Incompatible option detected: %s=%d, %s!\n", @@ -288,6 +297,10 @@ int intel_uc_init(struct drm_i915_private *i915) if (!HAS_GUC(i915)) return -ENODEV; + /* Don't allow GuC submission on pre-Gen11 */ + if (USES_GUC_SUBMISSION(i915) && INTEL_GEN(i915) < 11) + return -EIO; + ret = intel_guc_init(guc); if (ret) return ret; From patchwork Fri Mar 29 22:10:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877807 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5A26213B5 for ; Fri, 29 Mar 2019 22:11:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4429C28E8F for ; Fri, 29 Mar 2019 22:11:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3358F292AE; Fri, 29 Mar 2019 22:11:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D30BA28E8F for ; Fri, 29 Mar 2019 22:11:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B24A26E54D; Fri, 29 Mar 2019 22:11:31 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id C6E3E6E553 for ; Fri, 29 Mar 2019 22:11:28 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="287130451" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga004.jf.intel.com with ESMTP; 29 Mar 2019 15:11:27 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0S017079; Fri, 29 Mar 2019 22:11:26 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:10:50 +0000 Message-Id: <20190329221118.17308-3-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 02/30] drm/i915/guc: Simplify preparation of GuC parameter block X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Definition of the parameters block passed to GuC is about to change. Slightly refactor code now to make upcoming patch smaller. Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: John Spotswood Reviewed-by: John Spotswood Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_guc.c | 38 +++++++++++++++++++------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 3aabfa2d9198..c0e8b359b23a 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -333,19 +333,8 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc) return flags; } -/* - * Initialise the GuC parameter block before starting the firmware - * transfer. These parameters are read by the firmware on startup - * and cannot be changed thereafter. - */ -void intel_guc_init_params(struct intel_guc *guc) +static void guc_prepare_params(struct intel_guc *guc, u32 *params) { - struct drm_i915_private *dev_priv = guc_to_i915(guc); - u32 params[GUC_CTL_MAX_DWORDS]; - int i; - - memset(params, 0, sizeof(params)); - /* * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one * second. This ARAR is calculated by: @@ -360,9 +349,12 @@ void intel_guc_init_params(struct intel_guc *guc) params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc); +} - for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) - DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]); +static void guc_write_params(struct intel_guc *guc, const u32 *params) +{ + struct drm_i915_private *dev_priv = guc_to_i915(guc); + int i; /* * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and @@ -373,12 +365,28 @@ void intel_guc_init_params(struct intel_guc *guc) I915_WRITE(SOFT_SCRATCH(0), 0); - for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) + for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) { + DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]); I915_WRITE(SOFT_SCRATCH(1 + i), params[i]); + } intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_BLITTER); } +/* + * Initialise the GuC parameter block before starting the firmware + * transfer. These parameters are read by the firmware on startup + * and cannot be changed thereafter. + */ +void intel_guc_init_params(struct intel_guc *guc) +{ + u32 params[GUC_CTL_MAX_DWORDS]; + + memset(params, 0, sizeof(params)); + guc_prepare_params(guc, params); + guc_write_params(guc, params); +} + int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len, u32 *response_buf, u32 response_buf_size) { From patchwork Fri Mar 29 22:10:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877813 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7588713B5 for ; Fri, 29 Mar 2019 22:11:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 61A7E28E8F for ; Fri, 29 Mar 2019 22:11:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 563C8292AE; Fri, 29 Mar 2019 22:11:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EA76028E8F for ; Fri, 29 Mar 2019 22:11:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A3BDF6E558; Fri, 29 Mar 2019 22:11:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id C7BBD6E54D for ; Fri, 29 Mar 2019 22:11:30 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="138452994" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga003.jf.intel.com with ESMTP; 29 Mar 2019 15:11:28 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0T017079; Fri, 29 Mar 2019 22:11:27 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:10:51 +0000 Message-Id: <20190329221118.17308-4-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 03/30] drm/i915/guc: Update GuC firmware versions and names X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP GuC firmware changed its release version numbering schema and now it also includes patch version. Update our GuC firmware path definitions to match new pattern: _guc_...bin While here, reorder platform checks and start from the latest. Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Daniele Ceraolo Spurio Cc: Rodrigo Vivi Cc: Anusha Srivatsa Cc: Jeff Mcgee --- drivers/gpu/drm/i915/intel_guc_fw.c | 76 ++++++++++++++++------------- 1 file changed, 42 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c index 792a551450c7..c937a648c2a1 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/intel_guc_fw.c @@ -30,53 +30,61 @@ #include "intel_guc_fw.h" #include "i915_drv.h" -#define SKL_FW_MAJOR 9 -#define SKL_FW_MINOR 33 - -#define BXT_FW_MAJOR 9 -#define BXT_FW_MINOR 29 - -#define KBL_FW_MAJOR 9 -#define KBL_FW_MINOR 39 - -#define GUC_FW_PATH(platform, major, minor) \ - "i915/" __stringify(platform) "_guc_ver" __stringify(major) "_" __stringify(minor) ".bin" - -#define I915_SKL_GUC_UCODE GUC_FW_PATH(skl, SKL_FW_MAJOR, SKL_FW_MINOR) -MODULE_FIRMWARE(I915_SKL_GUC_UCODE); - -#define I915_BXT_GUC_UCODE GUC_FW_PATH(bxt, BXT_FW_MAJOR, BXT_FW_MINOR) -MODULE_FIRMWARE(I915_BXT_GUC_UCODE); - -#define I915_KBL_GUC_UCODE GUC_FW_PATH(kbl, KBL_FW_MAJOR, KBL_FW_MINOR) -MODULE_FIRMWARE(I915_KBL_GUC_UCODE); +#define __MAKE_GUC_FW_PATH(KEY) \ + "i915/" \ + __stringify(KEY##_GUC_FW_PREFIX) "_guc_" \ + __stringify(KEY##_GUC_FW_MAJOR) "." \ + __stringify(KEY##_GUC_FW_MINOR) "." \ + __stringify(KEY##_GUC_FW_PATCH) ".bin" + +#define SKL_GUC_FW_PREFIX skl +#define SKL_GUC_FW_MAJOR 32 +#define SKL_GUC_FW_MINOR 0 +#define SKL_GUC_FW_PATCH 3 +#define SKL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(SKL) + +#define BXT_GUC_FW_PREFIX bxt +#define BXT_GUC_FW_MAJOR 32 +#define BXT_GUC_FW_MINOR 0 +#define BXT_GUC_FW_PATCH 3 +#define BXT_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(BXT) + +#define KBL_GUC_FW_PREFIX kbl +#define KBL_GUC_FW_MAJOR 32 +#define KBL_GUC_FW_MINOR 0 +#define KBL_GUC_FW_PATCH 3 +#define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL) + +MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH); +MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH); +MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH); static void guc_fw_select(struct intel_uc_fw *guc_fw) { struct intel_guc *guc = container_of(guc_fw, struct intel_guc, fw); - struct drm_i915_private *dev_priv = guc_to_i915(guc); + struct drm_i915_private *i915 = guc_to_i915(guc); GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC); - if (!HAS_GUC(dev_priv)) + if (!HAS_GUC(i915)) return; if (i915_modparams.guc_firmware_path) { guc_fw->path = i915_modparams.guc_firmware_path; guc_fw->major_ver_wanted = 0; guc_fw->minor_ver_wanted = 0; - } else if (IS_SKYLAKE(dev_priv)) { - guc_fw->path = I915_SKL_GUC_UCODE; - guc_fw->major_ver_wanted = SKL_FW_MAJOR; - guc_fw->minor_ver_wanted = SKL_FW_MINOR; - } else if (IS_BROXTON(dev_priv)) { - guc_fw->path = I915_BXT_GUC_UCODE; - guc_fw->major_ver_wanted = BXT_FW_MAJOR; - guc_fw->minor_ver_wanted = BXT_FW_MINOR; - } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { - guc_fw->path = I915_KBL_GUC_UCODE; - guc_fw->major_ver_wanted = KBL_FW_MAJOR; - guc_fw->minor_ver_wanted = KBL_FW_MINOR; + } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) { + guc_fw->path = KBL_GUC_FIRMWARE_PATH; + guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR; + guc_fw->minor_ver_wanted = KBL_GUC_FW_MINOR; + } else if (IS_BROXTON(i915)) { + guc_fw->path = BXT_GUC_FIRMWARE_PATH; + guc_fw->major_ver_wanted = BXT_GUC_FW_MAJOR; + guc_fw->minor_ver_wanted = BXT_GUC_FW_MINOR; + } else if (IS_SKYLAKE(i915)) { + guc_fw->path = SKL_GUC_FIRMWARE_PATH; + guc_fw->major_ver_wanted = SKL_GUC_FW_MAJOR; + guc_fw->minor_ver_wanted = SKL_GUC_FW_MINOR; } } From patchwork Fri Mar 29 22:10:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877811 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8115917E0 for ; Fri, 29 Mar 2019 22:11:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6C2A428E8F for ; Fri, 29 Mar 2019 22:11:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 604CB292AE; Fri, 29 Mar 2019 22:11:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 01BC928E8F for ; Fri, 29 Mar 2019 22:11:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B36EE6E55A; Fri, 29 Mar 2019 22:11:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7372B6E54D for ; Fri, 29 Mar 2019 22:11:31 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="138602169" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga007.fm.intel.com with ESMTP; 29 Mar 2019 15:11:29 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0U017079; Fri, 29 Mar 2019 22:11:28 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:10:52 +0000 Message-Id: <20190329221118.17308-5-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 04/30] drm/i915/guc: Update GuC firmware CSS header X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP There are few minor changes in the CSS header related to the version numbering in new GuC firmwares. Update our definition and start using common tools for extracting bitfields. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen Cc: John Spotswood Cc: Jeff Mcgee --- drivers/gpu/drm/i915/intel_guc_fwif.h | 23 ++++++++--------------- drivers/gpu/drm/i915/intel_uc_fw.c | 20 ++++++++++---------- 2 files changed, 18 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index b2f5148f4f17..1cb4fad2d539 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -168,11 +168,7 @@ * in fw. So driver will load a truncated firmware in this case. * * HuC firmware layout is same as GuC firmware. - * - * HuC firmware css header is different. However, the only difference is where - * the version information is saved. The uc_css_header is unified to support - * both. Driver should get HuC version from uc_css_header.huc_sw_version, while - * uc_css_header.guc_sw_version for GuC. + * Only HuC version information is saved in a different way. */ struct uc_css_header { @@ -206,16 +202,13 @@ struct uc_css_header { char username[8]; char buildnumber[12]; - union { - struct { - u32 branch_client_version; - u32 sw_version; - } guc; - struct { - u32 sw_version; - u32 reserved; - } huc; - }; + u32 sw_version; +#define CSS_SW_VERSION_GUC_MAJOR (0xFF << 16) +#define CSS_SW_VERSION_GUC_MINOR (0xFF << 8) +#define CSS_SW_VERSION_GUC_PATCH (0xFF << 0) +#define CSS_SW_VERSION_HUC_MAJOR (0xFFFF << 16) +#define CSS_SW_VERSION_HUC_MINOR (0xFFFF << 0) + u32 sw_reserved; u32 prod_preprod_fw; u32 reserved[12]; u32 header_info; diff --git a/drivers/gpu/drm/i915/intel_uc_fw.c b/drivers/gpu/drm/i915/intel_uc_fw.c index becf05ebae4d..957c1feb30d3 100644 --- a/drivers/gpu/drm/i915/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/intel_uc_fw.c @@ -22,6 +22,7 @@ * */ +#include #include #include @@ -119,21 +120,20 @@ void intel_uc_fw_fetch(struct drm_i915_private *dev_priv, goto fail; } - /* - * The GuC firmware image has the version number embedded at a - * well-known offset within the firmware blob; note that major / minor - * version are TWO bytes each (i.e. u16), although all pointers and - * offsets are defined in terms of bytes (u8). - */ + /* Get version numbers from the CSS header */ switch (uc_fw->type) { case INTEL_UC_FW_TYPE_GUC: - uc_fw->major_ver_found = css->guc.sw_version >> 16; - uc_fw->minor_ver_found = css->guc.sw_version & 0xFFFF; + uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MAJOR, + css->sw_version); + uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_GUC_MINOR, + css->sw_version); break; case INTEL_UC_FW_TYPE_HUC: - uc_fw->major_ver_found = css->huc.sw_version >> 16; - uc_fw->minor_ver_found = css->huc.sw_version & 0xFFFF; + uc_fw->major_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MAJOR, + css->sw_version); + uc_fw->minor_ver_found = FIELD_GET(CSS_SW_VERSION_HUC_MINOR, + css->sw_version); break; default: From patchwork Fri Mar 29 22:10:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877833 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id BBFB713B5 for ; Fri, 29 Mar 2019 22:11:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A781628E8F for ; Fri, 29 Mar 2019 22:11:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9C06B292B4; Fri, 29 Mar 2019 22:11:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3157828E8F for ; Fri, 29 Mar 2019 22:11:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A440E6E561; Fri, 29 Mar 2019 22:11:45 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9497F6E553 for ; Fri, 29 Mar 2019 22:11:31 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="157084603" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga004.fm.intel.com with ESMTP; 29 Mar 2019 15:11:30 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0V017079; Fri, 29 Mar 2019 22:11:28 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:10:53 +0000 Message-Id: <20190329221118.17308-6-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 05/30] drm/i915/guc: Update GuC boot parameters X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP New GuC firmwares require updated boot parameters. Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Tvrtko Ursulin Cc: Daniele Ceraolo Spurio Cc: John Spotswood --- drivers/gpu/drm/i915/intel_guc.c | 36 +++++++++---------------- drivers/gpu/drm/i915/intel_guc_fwif.h | 39 +++++++-------------------- 2 files changed, 22 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index c0e8b359b23a..483c7019f817 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -243,14 +243,7 @@ void intel_guc_fini(struct intel_guc *guc) static u32 guc_ctl_debug_flags(struct intel_guc *guc) { u32 level = intel_guc_log_get_level(&guc->log); - u32 flags; - u32 ads; - - ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT; - flags = ads << GUC_ADS_ADDR_SHIFT | GUC_ADS_ENABLED; - - if (!GUC_LOG_LEVEL_IS_ENABLED(level)) - flags |= GUC_LOG_DEFAULT_DISABLED; + u32 flags = 0; if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) flags |= GUC_LOG_DISABLED; @@ -265,11 +258,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc) { u32 flags = 0; - flags |= GUC_CTL_VCS2_ENABLED; - - if (USES_GUC_SUBMISSION(guc_to_i915(guc))) - flags |= GUC_CTL_KERNEL_SUBMISSIONS; - else + if (!USES_GUC_SUBMISSION(guc_to_i915(guc))) flags |= GUC_CTL_DISABLE_SCHEDULER; return flags; @@ -333,22 +322,21 @@ static u32 guc_ctl_log_params_flags(struct intel_guc *guc) return flags; } -static void guc_prepare_params(struct intel_guc *guc, u32 *params) +static u32 guc_ctl_ads_flags(struct intel_guc *guc) { - /* - * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one - * second. This ARAR is calculated by: - * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10 - */ - params[GUC_CTL_ARAT_HIGH] = 0; - params[GUC_CTL_ARAT_LOW] = 100000000; + u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT; + u32 flags = ads << GUC_ADS_ADDR_SHIFT; - params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER; + return flags; +} +static void guc_prepare_params(struct intel_guc *guc, u32 *params) +{ + params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc); + params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); - params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); - params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc); + params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); } static void guc_write_params(struct intel_guc *guc, const u32 *params) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 1cb4fad2d539..64b56da9775c 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -73,44 +73,28 @@ #define GUC_STAGE_DESC_ATTR_PCH BIT(6) #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) -/* The guc control data is 10 DWORDs */ +/* New GuC control data */ #define GUC_CTL_CTXINFO 0 #define GUC_CTL_CTXNUM_IN16_SHIFT 0 #define GUC_CTL_BASE_ADDR_SHIFT 12 -#define GUC_CTL_ARAT_HIGH 1 -#define GUC_CTL_ARAT_LOW 2 - -#define GUC_CTL_DEVICE_INFO 3 - -#define GUC_CTL_LOG_PARAMS 4 +#define GUC_CTL_LOG_PARAMS 1 #define GUC_LOG_VALID (1 << 0) #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) #define GUC_LOG_CRASH_SHIFT 4 -#define GUC_LOG_CRASH_MASK (0x1 << GUC_LOG_CRASH_SHIFT) +#define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT) #define GUC_LOG_DPC_SHIFT 6 #define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT) #define GUC_LOG_ISR_SHIFT 9 #define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT) #define GUC_LOG_BUF_ADDR_SHIFT 12 -#define GUC_CTL_PAGE_FAULT_CONTROL 5 - -#define GUC_CTL_WA 6 -#define GUC_CTL_WA_UK_BY_DRIVER (1 << 3) - -#define GUC_CTL_FEATURE 7 -#define GUC_CTL_VCS2_ENABLED (1 << 0) -#define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1) -#define GUC_CTL_FEATURE2 (1 << 2) -#define GUC_CTL_POWER_GATING (1 << 3) -#define GUC_CTL_DISABLE_SCHEDULER (1 << 4) -#define GUC_CTL_PREEMPTION_LOG (1 << 5) -#define GUC_CTL_ENABLE_SLPC (1 << 7) -#define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8) +#define GUC_CTL_WA 2 +#define GUC_CTL_FEATURE 3 +#define GUC_CTL_DISABLE_SCHEDULER (1 << 14) -#define GUC_CTL_DEBUG 8 +#define GUC_CTL_DEBUG 4 #define GUC_LOG_VERBOSITY_SHIFT 0 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) @@ -123,13 +107,10 @@ #define GUC_LOG_DESTINATION_MASK (3 << 4) #define GUC_LOG_DISABLED (1 << 6) #define GUC_PROFILE_ENABLED (1 << 7) -#define GUC_WQ_TRACK_ENABLED (1 << 8) -#define GUC_ADS_ENABLED (1 << 9) -#define GUC_LOG_DEFAULT_DISABLED (1 << 10) -#define GUC_ADS_ADDR_SHIFT 11 -#define GUC_ADS_ADDR_MASK 0xfffff800 -#define GUC_CTL_RSRVD 9 +#define GUC_CTL_ADS 5 +#define GUC_ADS_ADDR_SHIFT 1 +#define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT) #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ From patchwork Fri Mar 29 22:10:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877819 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6DB9A13B5 for ; Fri, 29 Mar 2019 22:11:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5A1D128E8F for ; Fri, 29 Mar 2019 22:11:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4EB7F292AE; Fri, 29 Mar 2019 22:11:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1386D28E8F for ; Fri, 29 Mar 2019 22:11:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6DDC36E55D; Fri, 29 Mar 2019 22:11:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id DE97D6E55B for ; Fri, 29 Mar 2019 22:11:32 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="311593022" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga005.jf.intel.com with ESMTP; 29 Mar 2019 15:11:31 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0W017079; Fri, 29 Mar 2019 22:11:29 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:10:54 +0000 Message-Id: <20190329221118.17308-7-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 06/30] drm/i915/guc: Update GuC sleep status values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP New GuC firmwares use updated sleep status definitions. Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Daniele Ceraolo Spurio Cc: John Spotswood --- drivers/gpu/drm/i915/intel_guc_fwif.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 64b56da9775c..25d57c819e3f 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -648,9 +648,9 @@ enum intel_guc_report_status { }; enum intel_guc_sleep_state_status { - INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0, - INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1, - INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2 + INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1, + INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2, + INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3 #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000 }; From patchwork Fri Mar 29 22:10:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877831 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A955B17E0 for ; Fri, 29 Mar 2019 22:11:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9691F28E8F for ; Fri, 29 Mar 2019 22:11:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8B26E292B4; Fri, 29 Mar 2019 22:11:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4DDF928E8F for ; Fri, 29 Mar 2019 22:11:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 01AA96E567; Fri, 29 Mar 2019 22:11:45 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 15C306E557 for ; Fri, 29 Mar 2019 22:11:33 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="145051431" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by FMSMGA003.fm.intel.com with ESMTP; 29 Mar 2019 15:11:31 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0X017079; Fri, 29 Mar 2019 22:11:30 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:10:55 +0000 Message-Id: <20190329221118.17308-8-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 07/30] drm/i915/guc: Update GuC sample-forcewake command X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP New GuC firmwares use different action code value for this command. Signed-off-by: Michal Wajdeczko Cc: John Spotswood Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_guc_fwif.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 25d57c819e3f..dd9d99dc2aca 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -620,7 +620,6 @@ enum intel_guc_action { INTEL_GUC_ACTION_DEFAULT = 0x0, INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2, INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3, - INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6, INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10, INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30, @@ -628,6 +627,7 @@ enum intel_guc_action { INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, + INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005, INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505, INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506, From patchwork Fri Mar 29 22:10:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877815 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6981F17E0 for ; Fri, 29 Mar 2019 22:11:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 55F1F28E8F for ; Fri, 29 Mar 2019 22:11:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4AC64292AE; Fri, 29 Mar 2019 22:11:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 07FF928E8F for ; Fri, 29 Mar 2019 22:11:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E76A66E555; Fri, 29 Mar 2019 22:11:35 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id D404C6E554 for ; Fri, 29 Mar 2019 22:11:34 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="127065355" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga007.jf.intel.com with ESMTP; 29 Mar 2019 15:11:32 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0Y017079; Fri, 29 Mar 2019 22:11:31 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:10:56 +0000 Message-Id: <20190329221118.17308-9-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 08/30] drm/i915/guc: Always ask GuC to update power domain states X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP With newer GuC firmware it is always ok to ask GuC to update power domain states. Make it an unconditional initialization step. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: John Spotswood --- drivers/gpu/drm/i915/intel_guc_submission.c | 4 ---- drivers/gpu/drm/i915/intel_uc.c | 8 ++++---- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index c4ad73980988..f5dc11536850 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -1316,10 +1316,6 @@ int intel_guc_submission_enable(struct intel_guc *guc) GEM_BUG_ON(!guc->execbuf_client); - err = intel_guc_sample_forcewake(guc); - if (err) - return err; - err = guc_clients_enable(guc); if (err) return err; diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 61d2a2910ef1..49b6341f6cb4 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -409,14 +409,14 @@ int intel_uc_init_hw(struct drm_i915_private *i915) goto err_communication; } + ret = intel_guc_sample_forcewake(guc); + if (ret) + goto err_communication; + if (USES_GUC_SUBMISSION(i915)) { ret = intel_guc_submission_enable(guc); if (ret) goto err_communication; - } else if (INTEL_GEN(i915) < 11) { - ret = intel_guc_sample_forcewake(guc); - if (ret) - goto err_communication; } dev_info(i915->drm.dev, "GuC firmware version %u.%u\n", From patchwork Fri Mar 29 22:10:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877823 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 20688186D for ; Fri, 29 Mar 2019 22:11:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0AC532906F for ; Fri, 29 Mar 2019 22:11:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F3427292B4; Fri, 29 Mar 2019 22:11:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3383C2906F for ; Fri, 29 Mar 2019 22:11:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CE2436E55E; Fri, 29 Mar 2019 22:11:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id E42026E554 for ; Fri, 29 Mar 2019 22:11:35 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="129886216" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga008.jf.intel.com with ESMTP; 29 Mar 2019 15:11:33 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0Z017079; Fri, 29 Mar 2019 22:11:32 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:10:57 +0000 Message-Id: <20190329221118.17308-10-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 09/30] drm/i915/guc: Update GuC ADS object definition X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP New GuC firmwares use updated definitions for the Additional Data Structures (ADS). Signed-off-by: Michal Wajdeczko Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Fernando Pacheco Cc: Joonas Lahtinen Cc: John Spotswood Cc: Tomasz Lis --- drivers/gpu/drm/i915/intel_engine_cs.c | 5 ++ drivers/gpu/drm/i915/intel_guc_ads.c | 94 +++++++++++++++---------- drivers/gpu/drm/i915/intel_guc_fwif.h | 89 +++++++++++++---------- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 + 4 files changed, 117 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index d0427c2e3997..f777afc33d8a 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -231,6 +231,11 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class) } } +u32 intel_class_context_size(struct drm_i915_private *dev_priv, u8 class) +{ + return __intel_engine_context_size(dev_priv, class); +} + static u32 __engine_mmio_base(struct drm_i915_private *i915, const struct engine_mmio_base *bases) { diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c index bec62f34b15a..abab5cb6909a 100644 --- a/drivers/gpu/drm/i915/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/intel_guc_ads.c @@ -51,7 +51,7 @@ static void guc_policies_init(struct guc_policies *policies) policies->max_num_work_items = POLICY_MAX_NUM_WI; for (p = 0; p < GUC_CLIENT_PRIORITY_NUM; p++) { - for (i = GUC_RENDER_ENGINE; i < GUC_MAX_ENGINES_NUM; i++) { + for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++) { policy = &policies->policy[p][i]; guc_policy_init(policy); @@ -61,6 +61,11 @@ static void guc_policies_init(struct guc_policies *policies) policies->is_valid = 1; } +static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num) +{ + memset(pool, 0, num * sizeof(*pool)); +} + /* * The first 80 dwords of the register state context, containing the * execlists and ppgtt registers. @@ -75,20 +80,21 @@ static void guc_policies_init(struct guc_policies *policies) int intel_guc_ads_create(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); - struct i915_vma *vma, *kernel_ctx_vma; - struct page *page; + struct i915_vma *vma; /* The ads obj includes the struct itself and buffers passed to GuC */ struct { struct guc_ads ads; struct guc_policies policies; struct guc_mmio_reg_state reg_state; + struct guc_gt_system_info system_info; + struct guc_clients_info clients_info; + struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE]; u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE]; } __packed *blob; - struct intel_engine_cs *engine; - enum intel_engine_id id; - const u32 skipped_offset = LRC_HEADER_PAGES * PAGE_SIZE; const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE; u32 base; + u8 engine_class; + int ret; GEM_BUG_ON(guc->ads_vma); @@ -98,51 +104,67 @@ int intel_guc_ads_create(struct intel_guc *guc) guc->ads_vma = vma; - page = i915_vma_first_page(vma); - blob = kmap(page); + blob = i915_gem_object_pin_map(guc->ads_vma->obj, I915_MAP_WB); + if (IS_ERR(blob)) { + ret = PTR_ERR(blob); + goto err_vma; + } /* GuC scheduling policies */ guc_policies_init(&blob->policies); - /* MMIO reg state */ - for_each_engine(engine, dev_priv, id) { - blob->reg_state.white_list[engine->guc_id].mmio_start = - engine->mmio_base + GUC_MMIO_WHITE_LIST_START; - - /* Nothing to be saved or restored for now. */ - blob->reg_state.white_list[engine->guc_id].count = 0; - } - /* - * The GuC requires a "Golden Context" when it reinitialises - * engines after a reset. Here we use the Render ring default - * context, which must already exist and be pinned in the GGTT, - * so its address won't change after we've told the GuC where - * to find it. Note that we have to skip our header (1 page), - * because our GuC shared data is there. + * GuC expects a per-engine-class context image and size + * (minus hwsp and ring context). The context image will be + * used to reinitialize engines after a reset. It must exist + * and be pinned in the GGTT, so that the address won't change after + * we have told GuC where to find it. The context size will be used + * to validate that the LRC base + size fall within allowed GGTT. */ - kernel_ctx_vma = dev_priv->engine[RCS0]->kernel_context->state; - blob->ads.golden_context_lrca = - intel_guc_ggtt_offset(guc, kernel_ctx_vma) + skipped_offset; + for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS; ++engine_class) { + if (engine_class == OTHER_CLASS) + continue; + /* + * TODO: Set context pointer to default state to allow + * GuC to re-init guilty contexts after internal reset. + */ + blob->ads.golden_context_lrca[engine_class] = 0; + blob->ads.eng_state_size[engine_class] = + intel_class_context_size(dev_priv, engine_class) - skipped_size; + } - /* - * The GuC expects us to exclude the portion of the context image that - * it skips from the size it is to read. It starts reading from after - * the execlist context (so skipping the first page [PPHWSP] and 80 - * dwords). Weird guc is weird. - */ - for_each_engine(engine, dev_priv, id) - blob->ads.eng_state_size[engine->guc_id] = - engine->context_size - skipped_size; + /* System info */ + blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask); + blob->system_info.rcs_enabled = 1; + blob->system_info.bcs_enabled = 1; + + blob->system_info.vdbox_enable_mask = VDBOX_MASK(dev_priv); + blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv); + blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access; base = intel_guc_ggtt_offset(guc, vma); + + /* Clients info */ + guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool)); + + blob->clients_info.clients_num = 1; + blob->clients_info.ct_pool_addr = base + ptr_offset(blob, ct_pool); + blob->clients_info.ct_pool_count = ARRAY_SIZE(blob->ct_pool); + + /* ADS */ blob->ads.scheduler_policies = base + ptr_offset(blob, policies); blob->ads.reg_state_buffer = base + ptr_offset(blob, reg_state_buffer); blob->ads.reg_state_addr = base + ptr_offset(blob, reg_state); + blob->ads.gt_system_info = base + ptr_offset(blob, system_info); + blob->ads.clients_info = base + ptr_offset(blob, clients_info); - kunmap(page); + i915_gem_object_unpin_map(guc->ads_vma->obj); return 0; + +err_vma: + i915_vma_unpin_and_release(&guc->ads_vma, 0); + return ret; } void intel_guc_ads_destroy(struct intel_guc *guc) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index dd9d99dc2aca..68dfeecf7b26 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -39,6 +39,9 @@ #define GUC_VIDEO_ENGINE2 4 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) +#define GUC_MAX_ENGINE_CLASSES 5 +#define GUC_MAX_INSTANCES_PER_CLASS 4 + #define GUC_DOORBELL_INVALID 256 #define GUC_DB_SIZE (PAGE_SIZE) @@ -397,23 +400,19 @@ struct guc_ct_buffer_desc { struct guc_policy { /* Time for one workload to execute. (in micro seconds) */ u32 execution_quantum; - u32 reserved1; - /* Time to wait for a preemption request to completed before issuing a * reset. (in micro seconds). */ u32 preemption_time; - /* How much time to allow to run after the first fault is observed. * Then preempt afterwards. (in micro seconds) */ u32 fault_time; - u32 policy_flags; - u32 reserved[2]; + u32 reserved[8]; } __packed; struct guc_policies { - struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINES_NUM]; - + struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES]; + u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES]; /* In micro seconds. How much time to allow before DPC processing is * called back via interrupt (to prevent DPC queue drain starving). * Typically 1000s of micro seconds (example only, not granularity). */ @@ -426,57 +425,73 @@ struct guc_policies { * idle. */ u32 max_num_work_items; - u32 reserved[19]; + u32 reserved[4]; } __packed; /* GuC MMIO reg state struct */ -#define GUC_REGSET_FLAGS_NONE 0x0 -#define GUC_REGSET_POWERCYCLE 0x1 -#define GUC_REGSET_MASKED 0x2 -#define GUC_REGSET_ENGINERESET 0x4 -#define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8 -#define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 -#define GUC_REGSET_MAX_REGISTERS 25 -#define GUC_MMIO_WHITE_LIST_START 0x24d0 -#define GUC_MMIO_WHITE_LIST_MAX 12 +#define GUC_REGSET_MAX_REGISTERS 64 #define GUC_S3_SAVE_SPACE_PAGES 10 -struct guc_mmio_regset { - struct __packed { - u32 offset; - u32 value; - u32 flags; - } registers[GUC_REGSET_MAX_REGISTERS]; +struct guc_mmio_reg { + u32 offset; + u32 value; + u32 flags; +#define GUC_REGSET_MASKED (1 << 0) +} __packed; +struct guc_mmio_regset { + struct guc_mmio_reg registers[GUC_REGSET_MAX_REGISTERS]; u32 values_valid; u32 number_of_registers; } __packed; -/* MMIO registers that are set as non privileged */ -struct mmio_white_list { - u32 mmio_start; - u32 offsets[GUC_MMIO_WHITE_LIST_MAX]; - u32 count; +/* GuC register sets */ +struct guc_mmio_reg_state { + struct guc_mmio_regset engine_reg[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; + u32 reserved[98]; } __packed; -struct guc_mmio_reg_state { - struct guc_mmio_regset global_reg; - struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM]; - struct mmio_white_list white_list[GUC_MAX_ENGINES_NUM]; +/* HW info */ +struct guc_gt_system_info { + u32 slice_enabled; + u32 rcs_enabled; + u32 reserved0; + u32 bcs_enabled; + u32 vdbox_enable_mask; + u32 vdbox_sfc_support_mask; + u32 vebox_enable_mask; + u32 reserved[9]; } __packed; -/* GuC Additional Data Struct */ +/* Clients info */ +struct guc_ct_pool_entry { + struct guc_ct_buffer_desc desc; + u32 reserved[7]; +} __packed; +#define GUC_CT_POOL_SIZE 2 + +struct guc_clients_info { + u32 clients_num; + u32 reserved0[13]; + u32 ct_pool_addr; + u32 ct_pool_count; + u32 reserved[4]; +} __packed; + +/* GuC Additional Data Struct */ struct guc_ads { u32 reg_state_addr; u32 reg_state_buffer; - u32 golden_context_lrca; u32 scheduler_policies; - u32 reserved0[3]; - u32 eng_state_size[GUC_MAX_ENGINES_NUM]; - u32 reserved2[4]; + u32 gt_system_info; + u32 clients_info; + u32 control_data; + u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES]; + u32 eng_state_size[GUC_MAX_ENGINE_CLASSES]; + u32 reserved[16]; } __packed; /* GuC logging structures */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index e58d6f04177b..ae933b4e2044 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -548,6 +548,8 @@ ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine); struct i915_request * intel_engine_find_active_request(struct intel_engine_cs *engine); +u32 intel_class_context_size(struct drm_i915_private *dev_priv, u8 class); + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) static inline bool inject_preempt_hang(struct intel_engine_execlists *execlists) From patchwork Fri Mar 29 22:10:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877825 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8900A13B5 for ; Fri, 29 Mar 2019 22:11:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 73FD428E8F for ; Fri, 29 Mar 2019 22:11:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6893B292B4; Fri, 29 Mar 2019 22:11:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9912A28E8F for ; Fri, 29 Mar 2019 22:11:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 31BEB6E564; Fri, 29 Mar 2019 22:11:45 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 13C2A6E55B for ; Fri, 29 Mar 2019 22:11:37 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="131394473" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga006.jf.intel.com with ESMTP; 29 Mar 2019 15:11:34 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0a017079; Fri, 29 Mar 2019 22:11:33 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:10:58 +0000 Message-Id: <20190329221118.17308-11-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 10/30] drm/i915/guc: Reset GuC ADS during sanitize X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP GuC stores some data in there, which might be stale after a reset. Reinitialize whole ADS in case any part of it was corrupted during previous GuC run. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: MichaĹ Winiarski Cc: Tomasz Lis --- drivers/gpu/drm/i915/intel_guc.h | 2 + drivers/gpu/drm/i915/intel_guc_ads.c | 85 ++++++++++++++++++---------- drivers/gpu/drm/i915/intel_guc_ads.h | 1 + 3 files changed, 57 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 2c59ff8d9f39..4f3cf8eddfe6 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -26,6 +26,7 @@ #define _INTEL_GUC_H_ #include "intel_uncore.h" +#include "intel_guc_ads.h" #include "intel_guc_fw.h" #include "intel_guc_fwif.h" #include "intel_guc_ct.h" @@ -177,6 +178,7 @@ u32 intel_guc_reserved_gtt_size(struct intel_guc *guc); static inline int intel_guc_sanitize(struct intel_guc *guc) { intel_uc_fw_sanitize(&guc->fw); + intel_guc_ads_reset(guc); return 0; } diff --git a/drivers/gpu/drm/i915/intel_guc_ads.c b/drivers/gpu/drm/i915/intel_guc_ads.c index abab5cb6909a..97926effb944 100644 --- a/drivers/gpu/drm/i915/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/intel_guc_ads.c @@ -72,43 +72,28 @@ static void guc_ct_pool_entries_init(struct guc_ct_pool_entry *pool, u32 num) */ #define LR_HW_CONTEXT_SIZE (80 * sizeof(u32)) -/** - * intel_guc_ads_create() - creates GuC ADS - * @guc: intel_guc struct - * - */ -int intel_guc_ads_create(struct intel_guc *guc) +/* The ads obj includes the struct itself and buffers passed to GuC */ +struct __guc_ads_blob { + struct guc_ads ads; + struct guc_policies policies; + struct guc_mmio_reg_state reg_state; + struct guc_gt_system_info system_info; + struct guc_clients_info clients_info; + struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE]; + u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE]; +} __packed; + +static int __guc_ads_reinit(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); - struct i915_vma *vma; - /* The ads obj includes the struct itself and buffers passed to GuC */ - struct { - struct guc_ads ads; - struct guc_policies policies; - struct guc_mmio_reg_state reg_state; - struct guc_gt_system_info system_info; - struct guc_clients_info clients_info; - struct guc_ct_pool_entry ct_pool[GUC_CT_POOL_SIZE]; - u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE]; - } __packed *blob; + struct __guc_ads_blob *blob; const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE; u32 base; u8 engine_class; - int ret; - - GEM_BUG_ON(guc->ads_vma); - - vma = intel_guc_allocate_vma(guc, PAGE_ALIGN(sizeof(*blob))); - if (IS_ERR(vma)) - return PTR_ERR(vma); - - guc->ads_vma = vma; blob = i915_gem_object_pin_map(guc->ads_vma->obj, I915_MAP_WB); - if (IS_ERR(blob)) { - ret = PTR_ERR(blob); - goto err_vma; - } + if (IS_ERR(blob)) + return PTR_ERR(blob); /* GuC scheduling policies */ guc_policies_init(&blob->policies); @@ -142,7 +127,7 @@ int intel_guc_ads_create(struct intel_guc *guc) blob->system_info.vebox_enable_mask = VEBOX_MASK(dev_priv); blob->system_info.vdbox_sfc_support_mask = RUNTIME_INFO(dev_priv)->vdbox_sfc_access; - base = intel_guc_ggtt_offset(guc, vma); + base = intel_guc_ggtt_offset(guc, guc->ads_vma); /* Clients info */ guc_ct_pool_entries_init(blob->ct_pool, ARRAY_SIZE(blob->ct_pool)); @@ -161,6 +146,32 @@ int intel_guc_ads_create(struct intel_guc *guc) i915_gem_object_unpin_map(guc->ads_vma->obj); return 0; +} + +/** + * intel_guc_ads_create() - creates GuC ADS + * @guc: intel_guc struct + * + */ +int intel_guc_ads_create(struct intel_guc *guc) +{ + const u32 size = PAGE_ALIGN(sizeof(struct __guc_ads_blob)); + struct i915_vma *vma; + int ret; + + GEM_BUG_ON(guc->ads_vma); + + vma = intel_guc_allocate_vma(guc, size); + if (IS_ERR(vma)) + return PTR_ERR(vma); + + guc->ads_vma = vma; + + ret = __guc_ads_reinit(guc); + if (ret) + goto err_vma; + + return 0; err_vma: i915_vma_unpin_and_release(&guc->ads_vma, 0); @@ -171,3 +182,15 @@ void intel_guc_ads_destroy(struct intel_guc *guc) { i915_vma_unpin_and_release(&guc->ads_vma, 0); } + +/** + * intel_guc_ads_reset() - resets GuC ADS + * @guc: intel_guc struct + * + */ +void intel_guc_ads_reset(struct intel_guc *guc) +{ + if (!guc->ads_vma) + return; + __guc_ads_reinit(guc); +} diff --git a/drivers/gpu/drm/i915/intel_guc_ads.h b/drivers/gpu/drm/i915/intel_guc_ads.h index c4735742c564..7f40f9cd5fb9 100644 --- a/drivers/gpu/drm/i915/intel_guc_ads.h +++ b/drivers/gpu/drm/i915/intel_guc_ads.h @@ -29,5 +29,6 @@ struct intel_guc; int intel_guc_ads_create(struct intel_guc *guc); void intel_guc_ads_destroy(struct intel_guc *guc); +void intel_guc_ads_reset(struct intel_guc *guc); #endif From patchwork Fri Mar 29 22:10:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877829 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E16D717E0 for ; Fri, 29 Mar 2019 22:11:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF3EE28E8F for ; Fri, 29 Mar 2019 22:11:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C3A9C292B4; Fri, 29 Mar 2019 22:11:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7B7B528E8F for ; Fri, 29 Mar 2019 22:11:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5BA926E55F; Fri, 29 Mar 2019 22:11:45 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 133536E557 for ; Fri, 29 Mar 2019 22:11:37 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="156522295" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga002.fm.intel.com with ESMTP; 29 Mar 2019 15:11:35 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0b017079; Fri, 29 Mar 2019 22:11:34 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:10:59 +0000 Message-Id: <20190329221118.17308-12-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 11/30] drm/i915/guc: New GuC interrupt register for Gen11 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Gen11 defines new more flexible Host-to-GuC interrupt register. Now the host can write any 32-bit payload to trigger an interrupt and GuC can additionally read this payload from the register. Current GuC firmware ignores the payload so we just write 0. Bspec: 21043 Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen Cc: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_guc.c | 14 +++++++++++++- drivers/gpu/drm/i915/intel_guc_reg.h | 1 + 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 483c7019f817..5bc9bc7c956a 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -34,6 +34,13 @@ static void gen8_guc_raise_irq(struct intel_guc *guc) I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER); } +static void gen11_guc_raise_irq(struct intel_guc *guc) +{ + struct drm_i915_private *dev_priv = guc_to_i915(guc); + + I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0); +} + static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i) { GEM_BUG_ON(!guc->send_regs.base); @@ -63,6 +70,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc) void intel_guc_init_early(struct intel_guc *guc) { + struct drm_i915_private *i915 = guc_to_i915(guc); + intel_guc_fw_init_early(guc); intel_guc_ct_init_early(&guc->ct); intel_guc_log_init_early(&guc->log); @@ -71,7 +80,10 @@ void intel_guc_init_early(struct intel_guc *guc) spin_lock_init(&guc->irq_lock); guc->send = intel_guc_send_nop; guc->handler = intel_guc_to_host_event_handler_nop; - guc->notify = gen8_guc_raise_irq; + if (INTEL_GEN(i915) >= 11) + guc->notify = gen11_guc_raise_irq; + else + guc->notify = gen8_guc_raise_irq; } static int guc_init_wq(struct intel_guc *guc) diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h index 57e7ad522c2f..aec02eddbaed 100644 --- a/drivers/gpu/drm/i915/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/intel_guc_reg.h @@ -103,6 +103,7 @@ #define GUC_SEND_INTERRUPT _MMIO(0xc4c8) #define GUC_SEND_TRIGGER (1<<0) +#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0) #define GUC_NUM_DOORBELLS 256 From patchwork Fri Mar 29 22:11:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877817 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4A0A417E0 for ; Fri, 29 Mar 2019 22:11:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3635C28E8F for ; Fri, 29 Mar 2019 22:11:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2ABD6292AE; Fri, 29 Mar 2019 22:11:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D648628E8F for ; Fri, 29 Mar 2019 22:11:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6CFC46E554; Fri, 29 Mar 2019 22:11:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id B27836E554 for ; Fri, 29 Mar 2019 22:11:37 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="131394479" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga006.jf.intel.com with ESMTP; 29 Mar 2019 15:11:36 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0c017079; Fri, 29 Mar 2019 22:11:35 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:00 +0000 Message-Id: <20190329221118.17308-13-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 12/30] drm/i915/guc: New GuC scratch registers for Gen11 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Gen11 adds new set of scratch registers that can be used for MMIO based Host-to-Guc communication. Due to limited number of these registers it is expected that host will use them only for command transport buffers (CTB) communication setup if one is available. Bspec: 21044 Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen Cc: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_guc.c | 12 +++++++++--- drivers/gpu/drm/i915/intel_guc_reg.h | 3 +++ 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 5bc9bc7c956a..e54de551b567 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -56,9 +56,15 @@ void intel_guc_init_send_regs(struct intel_guc *guc) enum forcewake_domains fw_domains = 0; unsigned int i; - guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); - guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN; - BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT); + if (HAS_GUC_CT(dev_priv) && INTEL_GEN(dev_priv) >= 11) { + guc->send_regs.base = + i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0)); + guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT; + } else { + guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); + guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN; + BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT); + } for (i = 0; i < guc->send_regs.count; i++) { fw_domains |= intel_uncore_forcewake_for_reg(&dev_priv->uncore, diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h index aec02eddbaed..d26de5193568 100644 --- a/drivers/gpu/drm/i915/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/intel_guc_reg.h @@ -51,6 +51,9 @@ #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4) #define SOFT_SCRATCH_COUNT 16 +#define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4) +#define GEN11_SOFT_SCRATCH_COUNT 4 + #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4) #define UOS_RSA_SCRATCH_COUNT 64 From patchwork Fri Mar 29 22:11:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877827 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 12F2413B5 for ; Fri, 29 Mar 2019 22:11:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F1F0928E8F for ; Fri, 29 Mar 2019 22:11:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E6565292B4; Fri, 29 Mar 2019 22:11:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9F66028E8F for ; Fri, 29 Mar 2019 22:11:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CFA9A6E565; Fri, 29 Mar 2019 22:11:45 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 10EE96E554 for ; Fri, 29 Mar 2019 22:11:39 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="136017310" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga008.fm.intel.com with ESMTP; 29 Mar 2019 15:11:36 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0d017079; Fri, 29 Mar 2019 22:11:35 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:01 +0000 Message-Id: <20190329221118.17308-14-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 13/30] drm/i915/guc: Update GuC CTB response definition X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Oscar Mateo MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Oscar Mateo Current GuC firmwares identify response message in a different way. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Kelvin Gardiner Cc: John Spotswood --- drivers/gpu/drm/i915/intel_guc_ct.c | 2 +- drivers/gpu/drm/i915/intel_guc_fwif.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c index dde1dc0d6e69..2d5dc2aa22a7 100644 --- a/drivers/gpu/drm/i915/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/intel_guc_ct.c @@ -565,7 +565,7 @@ static inline unsigned int ct_header_get_action(u32 header) static inline bool ct_header_is_response(u32 header) { - return ct_header_get_action(header) == INTEL_GUC_ACTION_DEFAULT; + return !!(header & GUC_CT_MSG_IS_RESPONSE); } static int ctb_read(struct intel_guc_ct_buffer *ctb, u32 *data) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 68dfeecf7b26..115c693daf8e 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -361,6 +361,7 @@ struct guc_ct_buffer_desc { * * bit[4..0] message len (in dwords) * bit[7..5] reserved + * bit[8] response (G2H only) * bit[8] write fence to desc * bit[9] write status to H2G buff * bit[10] send status (via G2H) @@ -369,6 +370,7 @@ struct guc_ct_buffer_desc { */ #define GUC_CT_MSG_LEN_SHIFT 0 #define GUC_CT_MSG_LEN_MASK 0x1F +#define GUC_CT_MSG_IS_RESPONSE (1 << 8) #define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8) #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9) #define GUC_CT_MSG_SEND_STATUS (1 << 10) From patchwork Fri Mar 29 22:11:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877821 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6887613B5 for ; Fri, 29 Mar 2019 22:11:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 557AF28E8F for ; Fri, 29 Mar 2019 22:11:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4A740292B4; Fri, 29 Mar 2019 22:11:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9BF7928E8F for ; Fri, 29 Mar 2019 22:11:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 398CF6E557; Fri, 29 Mar 2019 22:11:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2525B6E554 for ; Fri, 29 Mar 2019 22:11:40 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="311593048" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga005.jf.intel.com with ESMTP; 29 Mar 2019 15:11:38 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0e017079; Fri, 29 Mar 2019 22:11:36 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:02 +0000 Message-Id: <20190329221118.17308-15-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 14/30] drm/i915/guc: Enable GuC CTB communication on Gen11 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Gen11 GuC firmware expects H2G command messages to be sent over CTB (command transport buffers). Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen Cc: John Spotswood --- drivers/gpu/drm/i915/i915_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index a7e1611af26d..112cfaacc013 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -720,6 +720,7 @@ static const struct intel_device_info intel_cannonlake_info = { }, \ GEN(11), \ .ddb_size = 2048, \ + .has_guc_ct = 1, \ .has_logical_ring_elsq = 1, \ .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 } From patchwork Fri Mar 29 22:11:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877851 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A8FE413B5 for ; Fri, 29 Mar 2019 22:12:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9574128E8F for ; Fri, 29 Mar 2019 22:12:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 89FEB292AE; Fri, 29 Mar 2019 22:12:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 30BF428E8F for ; Fri, 29 Mar 2019 22:12:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E00956E574; Fri, 29 Mar 2019 22:12:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7A6E46E554 for ; Fri, 29 Mar 2019 22:11:41 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="157084632" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga004.fm.intel.com with ESMTP; 29 Mar 2019 15:11:38 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0f017079; Fri, 29 Mar 2019 22:11:37 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:03 +0000 Message-Id: <20190329221118.17308-16-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 15/30] drm/i915/huc: New HuC status register for Gen11 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Gen11 defines new register for checking HuC authentication status. Look into the right register and bit. BSpec: 19686 Signed-off-by: Michal Wajdeczko Cc: Joonas Lahtinen Cc: Rodrigo Vivi Cc: Tony Ye Cc: Vinay Belgaumkar Cc: John Spotswood Cc: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_guc_reg.h | 3 ++ drivers/gpu/drm/i915/intel_huc.c | 56 ++++++++++++++++++++++++---- 2 files changed, 51 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h index d26de5193568..7eba65795b58 100644 --- a/drivers/gpu/drm/i915/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/intel_guc_reg.h @@ -79,6 +79,9 @@ #define HUC_STATUS2 _MMIO(0xD3B0) #define HUC_FW_VERIFIED (1<<7) +#define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xC1DC) +#define HUC_LOAD_SUCCESSFUL (1 << 0) + #define GUC_WOPCM_SIZE _MMIO(0xc050) #define GUC_WOPCM_SIZE_LOCKED (1<<0) #define GUC_WOPCM_SIZE_SHIFT 12 diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c index 94c04f16a2ad..708a4b387259 100644 --- a/drivers/gpu/drm/i915/intel_huc.c +++ b/drivers/gpu/drm/i915/intel_huc.c @@ -40,6 +40,47 @@ int intel_huc_init_misc(struct intel_huc *huc) return 0; } +static int gen8_huc_wait_verified(struct intel_huc *huc) +{ + struct drm_i915_private *i915 = huc_to_i915(huc); + u32 status; + int ret; + + ret = __intel_wait_for_register(&i915->uncore, + HUC_STATUS2, + HUC_FW_VERIFIED, + HUC_FW_VERIFIED, + 2, 50, &status); + if (ret) + DRM_ERROR("HuC: status %#x\n", status); + return ret; +} + +static int gen11_huc_wait_verified(struct intel_huc *huc) +{ + struct drm_i915_private *i915 = huc_to_i915(huc); + int ret; + + ret = __intel_wait_for_register(&i915->uncore, + GEN11_HUC_KERNEL_LOAD_INFO, + HUC_LOAD_SUCCESSFUL, + HUC_LOAD_SUCCESSFUL, + 2, 50, NULL); + return ret; +} + +static int huc_wait_verified(struct intel_huc *huc) +{ + struct drm_i915_private *i915 = huc_to_i915(huc); + int ret; + + if (INTEL_GEN(i915) >= 11) + ret = gen11_huc_wait_verified(huc); + else + ret = gen8_huc_wait_verified(huc); + return ret; +} + /** * intel_huc_auth() - Authenticate HuC uCode * @huc: intel_huc structure @@ -56,7 +97,6 @@ int intel_huc_auth(struct intel_huc *huc) struct drm_i915_private *i915 = huc_to_i915(huc); struct intel_guc *guc = &i915->guc; struct i915_vma *vma; - u32 status; int ret; if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) @@ -79,13 +119,9 @@ int intel_huc_auth(struct intel_huc *huc) } /* Check authentication status, it should be done by now */ - ret = __intel_wait_for_register(&i915->uncore, - HUC_STATUS2, - HUC_FW_VERIFIED, - HUC_FW_VERIFIED, - 2, 50, &status); + ret = huc_wait_verified(huc); if (ret) { - DRM_ERROR("HuC: Firmware not verified %#x\n", status); + DRM_ERROR("HuC: Firmware not verified %d\n", ret); goto fail_unpin; } @@ -122,7 +158,11 @@ int intel_huc_check_status(struct intel_huc *huc) return -ENODEV; with_intel_runtime_pm(dev_priv, wakeref) - status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED; + if (INTEL_GEN(dev_priv) >= 11) + status = I915_READ(GEN11_HUC_KERNEL_LOAD_INFO) & + HUC_LOAD_SUCCESSFUL; + else + status = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED; return status; } From patchwork Fri Mar 29 22:11:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877837 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C145186D for ; Fri, 29 Mar 2019 22:11:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 37734292B4 for ; Fri, 29 Mar 2019 22:11:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2BBA6292B6; Fri, 29 Mar 2019 22:11:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D1574292AE for ; Fri, 29 Mar 2019 22:11:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F00896E562; Fri, 29 Mar 2019 22:11:44 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8C17B6E557 for ; Fri, 29 Mar 2019 22:11:41 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="131394492" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga006.jf.intel.com with ESMTP; 29 Mar 2019 15:11:39 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0g017079; Fri, 29 Mar 2019 22:11:38 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:04 +0000 Message-Id: <20190329221118.17308-17-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 16/30] drm/i915/guc: Define GuC firmware version for Icelake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Define GuC firmware version for Icelake. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen Cc: Rodrigo Vivi Cc: Anusha Srivatsa --- drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c index c937a648c2a1..c88a089885a0 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/intel_guc_fw.c @@ -55,9 +55,16 @@ #define KBL_GUC_FW_PATCH 3 #define KBL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(KBL) +#define ICL_GUC_FW_PREFIX icl +#define ICL_GUC_FW_MAJOR 32 +#define ICL_GUC_FW_MINOR 0 +#define ICL_GUC_FW_PATCH 3 +#define ICL_GUC_FIRMWARE_PATH __MAKE_GUC_FW_PATH(ICL) + MODULE_FIRMWARE(SKL_GUC_FIRMWARE_PATH); MODULE_FIRMWARE(BXT_GUC_FIRMWARE_PATH); MODULE_FIRMWARE(KBL_GUC_FIRMWARE_PATH); +MODULE_FIRMWARE(ICL_GUC_FIRMWARE_PATH); static void guc_fw_select(struct intel_uc_fw *guc_fw) { @@ -73,6 +80,10 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw) guc_fw->path = i915_modparams.guc_firmware_path; guc_fw->major_ver_wanted = 0; guc_fw->minor_ver_wanted = 0; + } else if (IS_ICELAKE(i915)) { + guc_fw->path = ICL_GUC_FIRMWARE_PATH; + guc_fw->major_ver_wanted = ICL_GUC_FW_MAJOR; + guc_fw->minor_ver_wanted = ICL_GUC_FW_MINOR; } else if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915)) { guc_fw->path = KBL_GUC_FIRMWARE_PATH; guc_fw->major_ver_wanted = KBL_GUC_FW_MAJOR; From patchwork Fri Mar 29 22:11:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877835 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A8BED13B5 for ; Fri, 29 Mar 2019 22:11:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 95AE628E8F for ; Fri, 29 Mar 2019 22:11:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8A009292B4; Fri, 29 Mar 2019 22:11:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 347D528E8F for ; Fri, 29 Mar 2019 22:11:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A6556E568; Fri, 29 Mar 2019 22:11:46 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47D3E6E554 for ; Fri, 29 Mar 2019 22:11:42 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="138602200" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga007.fm.intel.com with ESMTP; 29 Mar 2019 15:11:40 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0h017079; Fri, 29 Mar 2019 22:11:39 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:05 +0000 Message-Id: <20190329221118.17308-18-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 17/30] drm/i915/huc: Define HuC firmware version for Icelake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the support to load HuC on ICL. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen Cc: Anusha Srivatsa Cc: Tony Ye --- drivers/gpu/drm/i915/intel_huc_fw.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_huc_fw.c b/drivers/gpu/drm/i915/intel_huc_fw.c index 68d47c105939..b8e160dc4621 100644 --- a/drivers/gpu/drm/i915/intel_huc_fw.c +++ b/drivers/gpu/drm/i915/intel_huc_fw.c @@ -34,6 +34,10 @@ #define KBL_HUC_FW_MINOR 00 #define KBL_BLD_NUM 1810 +#define ICL_HUC_FW_MAJOR 8 +#define ICL_HUC_FW_MINOR 4 +#define ICL_BLD_NUM 3132 + #define HUC_FW_PATH(platform, major, minor, bld_num) \ "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \ __stringify(minor) "_" __stringify(bld_num) ".bin" @@ -50,6 +54,10 @@ MODULE_FIRMWARE(I915_BXT_HUC_UCODE); KBL_HUC_FW_MINOR, KBL_BLD_NUM) MODULE_FIRMWARE(I915_KBL_HUC_UCODE); +#define I915_ICL_HUC_UCODE HUC_FW_PATH(icl, ICL_HUC_FW_MAJOR, \ + ICL_HUC_FW_MINOR, ICL_BLD_NUM) +MODULE_FIRMWARE(I915_ICL_HUC_UCODE); + static void huc_fw_select(struct intel_uc_fw *huc_fw) { struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw); @@ -76,6 +84,10 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw) huc_fw->path = I915_KBL_HUC_UCODE; huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR; huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR; + } else if (IS_ICELAKE(dev_priv)) { + huc_fw->path = I915_ICL_HUC_UCODE; + huc_fw->major_ver_wanted = ICL_HUC_FW_MAJOR; + huc_fw->minor_ver_wanted = ICL_HUC_FW_MINOR; } } From patchwork Fri Mar 29 22:11:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877839 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 58B1B13B5 for ; Fri, 29 Mar 2019 22:11:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4617328E8F for ; Fri, 29 Mar 2019 22:11:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3A5C4292B9; Fri, 29 Mar 2019 22:11:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C983328E8F for ; Fri, 29 Mar 2019 22:11:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A2EDA6E56F; Fri, 29 Mar 2019 22:11:47 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id B10336E557 for ; Fri, 29 Mar 2019 22:11:43 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="218878591" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga001.jf.intel.com with ESMTP; 29 Mar 2019 15:11:41 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0i017079; Fri, 29 Mar 2019 22:11:40 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:06 +0000 Message-Id: <20190329221118.17308-19-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 18/30] drm/i915/guc: Treat GuC initialization failure as -EIO X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP There is no fallback to execlists, but instead of aborting whole driver load, just mark it as wedged. Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Tvrtko Ursulin Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 3 ++- drivers/gpu/drm/i915/intel_uc.c | 6 ++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index e506e43cfade..65f7c10b324a 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4947,7 +4947,8 @@ int i915_gem_init(struct drm_i915_private *dev_priv) mutex_lock(&dev_priv->drm.struct_mutex); intel_uc_fini_hw(dev_priv); err_uc_init: - intel_uc_fini(dev_priv); + if (ret != -EIO) + intel_uc_fini(dev_priv); err_pm: if (ret != -EIO) { intel_cleanup_gt_powersave(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 49b6341f6cb4..b516cc1ff18c 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -439,12 +439,10 @@ int intel_uc_init_hw(struct drm_i915_private *i915) /* * Note that there is no fallback as either user explicitly asked for * the GuC or driver default option was to run with the GuC enabled. + * Return -EIO to just disable GPU submission but keep KMS alive. */ - if (GEM_WARN_ON(ret == -EIO)) - ret = -EINVAL; - dev_err(i915->drm.dev, "GuC initialization failed %d\n", ret); - return ret; + return -EIO; } void intel_uc_fini_hw(struct drm_i915_private *i915) From patchwork Fri Mar 29 22:11:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877847 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AC36913B5 for ; Fri, 29 Mar 2019 22:12:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9753728E8F for ; Fri, 29 Mar 2019 22:12:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8BEDC292B4; Fri, 29 Mar 2019 22:12:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B8CBE28E8F for ; Fri, 29 Mar 2019 22:12:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 267C56E55B; Fri, 29 Mar 2019 22:12:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 52DFD6E56C for ; Fri, 29 Mar 2019 22:11:46 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="138453057" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga003.jf.intel.com with ESMTP; 29 Mar 2019 15:11:42 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0j017079; Fri, 29 Mar 2019 22:11:41 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:07 +0000 Message-Id: <20190329221118.17308-20-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 19/30] drm/i915/guc: New GuC IDs based on engine class and instance X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Oscar Mateo , Michel Thierry MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Daniele Ceraolo Spurio Starting from Gen11, the ID to be provided to GuC needs to contain the engine class in bits [0..2] and the instance in bits [3..6]. NOTE: this patch breaks pointer dereferences in some existing GuC functions that use the guc_id to dereference arrays but these functions are not used for now as we have GuC submission disabled and we will update these functions in follow up patch which requires new IDs. Bspec: 20944 Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Oscar Mateo Signed-off-by: Michel Thierry Signed-off-by: Rodrigo Vivi Signed-off-by: Michal Wajdeczko Cc: Michal Winiarski Cc: Tomasz Lis Cc: Joonas Lahtinen Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_engine_cs.c | 3 ++- drivers/gpu/drm/i915/intel_guc_fwif.h | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index f777afc33d8a..6e0efdd5d354 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -312,7 +312,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv, engine->i915 = dev_priv; engine->uncore = &dev_priv->uncore; __sprint_engine_name(engine->name, info); - engine->hw_id = engine->guc_id = info->hw_id; + engine->hw_id = info->hw_id; + engine->guc_id = MAKE_GUC_ID(info->class, info->instance); engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases); engine->class = info->class; engine->instance = info->instance; diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 115c693daf8e..61f718b907f3 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -117,6 +117,25 @@ #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ +/* + * The class goes in bits [0..2] of the GuC ID, the instance in bits [3..6]. + * Bit 7 can be used for operations that apply to all engine classes&instances. + */ +#define GUC_ENGINE_CLASS_SHIFT 0 +#define GUC_ENGINE_CLASS_MASK (0x7 << GUC_ENGINE_CLASS_SHIFT) +#define GUC_ENGINE_INSTANCE_SHIFT 3 +#define GUC_ENGINE_INSTANCE_MASK (0xf << GUC_ENGINE_INSTANCE_SHIFT) +#define GUC_ENGINE_ALL_INSTANCES (1 << 7) + +#define MAKE_GUC_ID(class, instance) \ + (((class) << GUC_ENGINE_CLASS_SHIFT) | \ + ((instance) << GUC_ENGINE_INSTANCE_SHIFT)) + +#define GUC_ID_TO_ENGINE_CLASS(guc_id) \ + (((guc_id) & GUC_ENGINE_CLASS_MASK) >> GUC_ENGINE_CLASS_SHIFT) +#define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \ + (((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT) + /** * DOC: GuC Firmware Layout * From patchwork Fri Mar 29 22:11:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877853 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 92C6B13B5 for ; Fri, 29 Mar 2019 22:12:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7CECF28E8F for ; Fri, 29 Mar 2019 22:12:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 71916292AE; Fri, 29 Mar 2019 22:12:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DF59428E8F for ; Fri, 29 Mar 2019 22:12:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1343E6E576; Fri, 29 Mar 2019 22:12:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3AE2F6E569 for ; Fri, 29 Mar 2019 22:11:46 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="157084670" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga004.fm.intel.com with ESMTP; 29 Mar 2019 15:11:43 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0k017079; Fri, 29 Mar 2019 22:11:42 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:08 +0000 Message-Id: <20190329221118.17308-21-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 20/30] drm/i915/guc: Make use of the SW counter field in the context descriptor X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Oscar Mateo MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Oscar Mateo The new context descriptor format contains two assignable fields: the SW Context ID (technically 11 bits, but practically limited to 2032 entries due to some being reserved for future use by the GuC) and the SW Counter (6 bits). We don't want to limit ourselves too much in the maximum number of concurrent contexts we want to allow, so ideally we want to employ every possible bit available. Unfortunately, a further limitation in the interface with the GuC means the combination of SW Context ID + SW Counter has to be unique within the same engine class (as we use the SW Context ID to index in the GuC stage descriptor pool, and the Engine Class + SW Counter to index in the 2-dimensional lrc array). This essentially means we need to somehow encode the engine instance. Since the BSpec allows 6 bits for engine instance, we use the whole SW counter for this task. If the limitation of 2032 maximum simultaneous contexts is too restrictive, we can always squeeze things a bit more (3 extras bits for hw_id, 3 bits for instance) and things will still work (Gen11 does not instance more than 8 engines of any class). Another alternative would be to generate the hw_id per HW context instead of per GEM context, but that has other problems (e.g. maximum number of user-created contexts would be variable, no relationship between a GuC principal descriptor and the proxy descriptor it uses, ...) Bspec: 12254 Signed-off-by: Oscar Mateo Signed-off-by: Rodrigo Vivi Signed-off-by: Michal Wajdeczko Signed-off-by: Daniele Ceraolo Spurio Cc: Joonas Lahtinen Cc: Lionel Landwerlin Cc: Michal Winiarski Cc: Tomasz Lis Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_drv.h | 9 ++++++++- drivers/gpu/drm/i915/i915_gem_context.c | 6 +++++- drivers/gpu/drm/i915/i915_perf.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_context_types.h | 2 ++ drivers/gpu/drm/i915/intel_lrc.c | 12 +++++++++--- 6 files changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f75600fa77c6..b3d5b715b637 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1758,14 +1758,21 @@ struct drm_i915_private { struct llist_head free_list; struct work_struct free_work; - /* The hw wants to have a stable context identifier for the + /* + * The HW wants to have a stable context identifier for the * lifetime of the context (for OA, PASID, faults, etc). * This is limited in execlists to 21 bits. + * In enhanced execlist (GEN11+) this is limited to 11 bits + * (the SW Context ID field) but GuC limits it further so + * without taking advantage of part of the SW counter field the + * firmware only supports a max number of contexts equal to the + * number of entries in the GuC stage descriptor pool. */ struct ida hw_ida; #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */ #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ +#define GEN11_MAX_CONTEXT_HW_ID_WITH_GUC GUC_MAX_STAGE_DESCRIPTORS struct list_head hw_id_list; } contexts; diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 662da485e15f..d882525f67a3 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -144,8 +144,12 @@ static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp) lockdep_assert_held(&i915->contexts.mutex); + BUILD_BUG_ON(GUC_MAX_STAGE_DESCRIPTORS > GEN11_MAX_CONTEXT_HW_ID); + if (INTEL_GEN(i915) >= 11) - max = GEN11_MAX_CONTEXT_HW_ID; + max = USES_GUC_SUBMISSION(i915) ? + GEN11_MAX_CONTEXT_HW_ID_WITH_GUC : + GEN11_MAX_CONTEXT_HW_ID; else if (USES_GUC_SUBMISSION(i915)) /* * When using GuC in proxy submission, GuC consumes the diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 39a4804091d7..08fb77333d85 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1292,6 +1292,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream) case 11: { i915->perf.oa.specific_ctx_id_mask = ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32) | + ((1U << GEN11_SW_COUNTER_WIDTH) - 1) << (GEN11_SW_COUNTER_SHIFT - 32) | ((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) | ((1 << GEN11_ENGINE_CLASS_WIDTH) - 1) << (GEN11_ENGINE_CLASS_SHIFT - 32); i915->perf.oa.specific_ctx_id = upper_32_bits(ce->lrc_desc); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 341f03e00536..8aee35ced574 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4008,6 +4008,8 @@ enum { #define GEN8_CTX_ID_WIDTH 21 #define GEN11_SW_CTX_ID_SHIFT 37 #define GEN11_SW_CTX_ID_WIDTH 11 +#define GEN11_SW_COUNTER_SHIFT 55 +#define GEN11_SW_COUNTER_WIDTH 6 #define GEN11_ENGINE_CLASS_SHIFT 61 #define GEN11_ENGINE_CLASS_WIDTH 3 #define GEN11_ENGINE_INSTANCE_SHIFT 48 diff --git a/drivers/gpu/drm/i915/intel_context_types.h b/drivers/gpu/drm/i915/intel_context_types.h index 624729a35875..af4183780271 100644 --- a/drivers/gpu/drm/i915/intel_context_types.h +++ b/drivers/gpu/drm/i915/intel_context_types.h @@ -53,6 +53,8 @@ struct intel_context { u32 *lrc_reg_state; u64 lrc_desc; + u32 sw_context_id; + u32 sw_counter; atomic_t pin_count; struct mutex pin_mutex; /* guards pinning and associated on-gpuing */ diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index bec232acc8d7..31db38560680 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -345,14 +345,15 @@ lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine) * anything below. */ if (INTEL_GEN(engine->i915) >= 11) { - GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH)); - desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT; + GEM_BUG_ON(ce->sw_context_id >= BIT(GEN11_SW_CTX_ID_WIDTH)); + desc |= (u64)ce->sw_context_id << GEN11_SW_CTX_ID_SHIFT; /* bits 37-47 */ desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT; /* bits 48-53 */ - /* TODO: decide what to do with SW counter (bits 55-60) */ + desc |= (u64)ce->sw_counter << GEN11_SW_COUNTER_SHIFT; + /* bits 55-60 */ desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT; /* bits 61-63 */ @@ -1358,6 +1359,11 @@ __execlists_context_pin(struct intel_context *ce, if (ret) goto unpin_ring; + if (INTEL_GEN(engine->i915) >= 11) { + ce->sw_context_id = ce->gem_context->hw_id; + ce->sw_counter = engine->instance; + } + ce->lrc_desc = lrc_descriptor(ce, engine); ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; __execlists_update_reg_state(ce, engine); From patchwork Fri Mar 29 22:11:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877841 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 84BAB13B5 for ; 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Fri, 29 Mar 2019 22:11:46 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="138602237" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga007.fm.intel.com with ESMTP; 29 Mar 2019 15:11:45 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0l017079; Fri, 29 Mar 2019 22:11:43 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:09 +0000 Message-Id: <20190329221118.17308-22-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 21/30] drm/i915/guc: New GuC stage descriptors X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Daniele Ceraolo Spurio With the new interface, GuC now requires every lrc to be registered in one of the stage descriptors, which have been re-designed so that each descriptor can store up to 64 lrc per class (i.e. equal to the possible SW counter values). Similarly to what happened with the previous legacy design, it is possible to have a single "proxy" descriptor that owns the workqueue and the doorbell and use it for all submission. To distinguish the proxy descriptors from the one used for lrc storage, the latter have been called "principal". A descriptor can't be both a proxy and a principal at the same time; to enforce this, since we only use 1 proxy descriptor per client, we reserve enough descriptor from the bottom of the pool to be used as proxy and leave the others as principals. For simplicity, we currently map context IDs 1:1 to principal descriptors, but we could have more contexts in flight if needed by using the SW counter. Note that the lrcs need to be mapped in the principal descriptor until GuC is done with them. This means that we can't release the HW id when the user app closes the ctx because it might still be in flight with GuC and that we need to be careful when unpinning because the fact that the a request on the next context has completed doesn't mean that GuC is done processing the first one. See in-code comments for details. NOTE: GuC is not going to look at lrcs that are not in flight, so we could potentially skip the unpinning steps. However, the unpining steps perform extra correctness check so better keep them until we're sure that the flow is solid. Based on an initial patch by Oscar Mateo. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Michal Wajdeczko Cc: Michal Winiarski Cc: Tomasz Lis Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_debugfs.c | 30 +- drivers/gpu/drm/i915/i915_drv.h | 5 +- drivers/gpu/drm/i915/i915_gem_context.c | 9 +- drivers/gpu/drm/i915/intel_guc.h | 14 +- drivers/gpu/drm/i915/intel_guc_fwif.h | 73 +++-- drivers/gpu/drm/i915/intel_guc_submission.c | 345 +++++++++++++++----- drivers/gpu/drm/i915/intel_lrc.c | 12 +- drivers/gpu/drm/i915/intel_lrc.h | 4 + drivers/gpu/drm/i915/selftests/intel_guc.c | 14 +- 9 files changed, 363 insertions(+), 143 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index f93a043f033a..24f983a21e87 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2259,11 +2259,10 @@ static int i915_guc_stage_pool(struct seq_file *m, void *data) seq_printf(m, "GuC stage descriptor %u:\n", index); seq_printf(m, "\tIndex: %u\n", desc->stage_id); + seq_printf(m, "\tProxy Index: %u\n", desc->proxy_id); seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute); seq_printf(m, "\tPriority: %d\n", desc->priority); seq_printf(m, "\tDoorbell id: %d\n", desc->db_id); - seq_printf(m, "\tEngines used: 0x%x\n", - desc->engines_used); seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n", desc->db_trigger_phy, desc->db_trigger_cpu, @@ -2275,18 +2274,21 @@ static int i915_guc_stage_pool(struct seq_file *m, void *data) seq_putc(m, '\n'); for_each_engine_masked(engine, dev_priv, client->engines, tmp) { - u32 guc_engine_id = engine->guc_id; - struct guc_execlist_context *lrc = - &desc->lrc[guc_engine_id]; - - seq_printf(m, "\t%s LRC:\n", engine->name); - seq_printf(m, "\t\tContext desc: 0x%x\n", - lrc->context_desc); - seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id); - seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca); - seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin); - seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end); - seq_putc(m, '\n'); + u8 class = engine->class; + u8 inst = engine->instance; + + if (desc->lrc_alloc_map[class].bitmap & BIT(inst)) { + struct guc_execlist_context *lrc = + &desc->lrc[class][inst]; + seq_printf(m, "\t%s LRC:\n", engine->name); + seq_printf(m, "\t\tHW context desc: 0x%x:0x%x\n", + lower_32_bits(lrc->hw_context_desc), + upper_32_bits(lrc->hw_context_desc)); + seq_printf(m, "\t\tLRC: 0x%x\n", lrc->ring_lrc); + seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin); + seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end); + seq_putc(m, '\n'); + } } } diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b3d5b715b637..3e7d0f3d2c82 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1766,13 +1766,14 @@ struct drm_i915_private { * (the SW Context ID field) but GuC limits it further so * without taking advantage of part of the SW counter field the * firmware only supports a max number of contexts equal to the - * number of entries in the GuC stage descriptor pool. + * number of entries in the GuC stage descriptor pool, minus + * the descriptors reserved for proxy usage */ struct ida hw_ida; #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */ #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ -#define GEN11_MAX_CONTEXT_HW_ID_WITH_GUC GUC_MAX_STAGE_DESCRIPTORS +#define GEN11_MAX_CONTEXT_HW_ID_WITH_GUC GUC_MAX_PPAL_STAGE_DESCRIPTORS struct list_head hw_id_list; } contexts; diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index d882525f67a3..74fa6610d532 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -308,10 +308,15 @@ static void context_close(struct i915_gem_context *ctx) i915_gem_context_set_closed(ctx); /* - * This context will never again be assinged to HW, so we can + * This context will never again be assigned to HW, so we can * reuse its ID for the next context. + * + * if GuC is in use, we need to keep the ID until GuC has finished + * processing all submitted requests because the ID is used by the + * firmware to index the guc stage_desc pool. */ - release_hw_id(ctx); + if (!USES_GUC_SUBMISSION(ctx->i915)) + release_hw_id(ctx); /* * The LUT uses the VMA as a backpointer to unref the object, diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 4f3cf8eddfe6..dbe4297f8a7d 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -59,10 +59,14 @@ struct intel_guc { bool interrupts_enabled; unsigned int msg_enabled_mask; + struct ida client_ids; +#define GUC_MAX_CLIENT_IDS 2 + struct i915_vma *ads_vma; struct i915_vma *stage_desc_pool; void *stage_desc_pool_vaddr; - struct ida stage_ids; +#define GUC_MAX_PPAL_STAGE_DESCRIPTORS (GUC_MAX_STAGE_DESCRIPTORS - GUC_MAX_CLIENT_IDS) + struct i915_vma *shared_data; void *shared_data_vaddr; @@ -95,6 +99,14 @@ struct intel_guc { /* GuC's FW specific notify function */ void (*notify)(struct intel_guc *guc); + + /* + * Override the first stage_desc to be used as proxy + * (Default: GUC_MAX_PPAL_STAGE_DESCRIPTORS). The max number of ppal + * descriptors is not updated accordingly since the test using this does + * not allocate any context. + */ + I915_SELFTEST_DECLARE(u32 starting_proxy_id); }; static inline bool intel_guc_is_alive(struct intel_guc *guc) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 61f718b907f3..a900680ff5a4 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -32,6 +32,8 @@ #define GUC_MAX_STAGE_DESCRIPTORS 1024 #define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS +#define GUC_MAX_LRC_PER_CLASS 64 + #define GUC_RENDER_ENGINE 0 #define GUC_VIDEO_ENGINE 1 #define GUC_BLITTER_ENGINE 2 @@ -68,9 +70,12 @@ #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT) #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) -#define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) -#define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) -#define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) +#define GUC_STAGE_DESC_ATTR_TYPE_SHIFT 1 +#define GUC_STAGE_DESC_ATTR_PRINCIPAL (0x0 << GUC_STAGE_DESC_ATTR_TYPE_SHIFT) +#define GUC_STAGE_DESC_ATTR_PROXY (0x1 << GUC_STAGE_DESC_ATTR_TYPE_SHIFT) +#define GUC_STAGE_DESC_ATTR_REAL (0x2 << GUC_STAGE_DESC_ATTR_TYPE_SHIFT) +#define GUC_STAGE_DESC_ATTR_TYPE_MASK (0x3 << GUC_STAGE_DESC_ATTR_TYPE_SHIFT) +#define GUC_STAGE_DESC_ATTR_KERNEL (1 << 3) #define GUC_STAGE_DESC_ATTR_RESET BIT(4) #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) #define GUC_STAGE_DESC_ATTR_PCH BIT(6) @@ -234,9 +239,10 @@ struct guc_process_desc { u64 wq_base_addr; u32 wq_size_bytes; u32 wq_status; - u32 engine_presence; u32 priority; - u32 reserved[30]; + u32 token; + u32 queue_engine_error; + u32 reserved[23]; } __packed; /* engine id and context id is packed into guc_execlist_context.context_id*/ @@ -245,18 +251,20 @@ struct guc_process_desc { /* The execlist context including software and HW information */ struct guc_execlist_context { - u32 context_desc; - u32 context_id; - u32 ring_status; - u32 ring_lrca; + u64 hw_context_desc; + u32 reserved0; + u32 ring_lrc; u32 ring_begin; u32 ring_end; u32 ring_next_free_location; u32 ring_current_tail_pointer_value; - u8 engine_state_submit_value; - u8 engine_state_wait_value; - u16 pagefault_count; - u16 engine_submit_queue_count; + u32 engine_state_wait_value; + u32 state_reserved; + u32 is_present_in_sq; + u32 sync_value; + u32 sync_addr; + u32 slpc_hints; + u32 reserved1[4]; } __packed; /* @@ -269,36 +277,33 @@ struct guc_execlist_context { * with the GuC, being allocated before the GuC is loaded with its firmware. */ struct guc_stage_desc { - u32 sched_common_area; + u64 desc_private; u32 stage_id; - u32 pas_id; - u8 engines_used; + u32 proxy_id; u64 db_trigger_cpu; u32 db_trigger_uk; u64 db_trigger_phy; - u16 db_id; - - struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM]; - - u8 attribute; - - u32 priority; - + u32 db_id; + struct guc_execlist_context lrc[GUC_MAX_ENGINE_CLASSES][GUC_MAX_LRC_PER_CLASS]; + struct { + u64 bitmap; + u32 reserved0; + } __packed lrc_alloc_map[GUC_MAX_ENGINE_CLASSES]; + u32 lrc_count; + u32 max_lrc_per_class; + u32 attribute; /* GUC_STAGE_DESC_ATTR_xxx */ + u32 priority; /* GUC_CLIENT_PRIORITY_xxx */ u32 wq_sampled_tail_offset; u32 wq_total_submit_enqueues; - u32 process_desc; u32 wq_addr; u32 wq_size; - - u32 engine_presence; - - u8 engine_suspended; - - u8 reserved0[3]; - u64 reserved1[1]; - - u64 desc_private; + u32 feature0; + u32 feature1; + u32 feature2; + u32 queue_engine_error; + u32 reserved[2]; + u64 reserved3[12]; } __packed; /** diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index f5dc11536850..3104f091abc5 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -46,17 +46,25 @@ * that contains all required pages for these elements). * * GuC stage descriptor: - * During initialization, the driver allocates a static pool of 1024 such - * descriptors, and shares them with the GuC. - * Currently, there exists a 1:1 mapping between a intel_guc_client and a - * guc_stage_desc (via the client's stage_id), so effectively only one - * gets used. This stage descriptor lets the GuC know about the doorbell, - * workqueue and process descriptor. Theoretically, it also lets the GuC - * know about our HW contexts (context ID, etc...), but we actually - * employ a kind of submission where the GuC uses the LRCA sent via the work - * item instead (the single guc_stage_desc associated to execbuf client - * contains information about the default kernel context only, but this is - * essentially unused). This is called a "proxy" submission. + * During initialization, the driver allocates a static pool of descriptors + * and shares them with the GuC. A stage descriptor lets the GuC know about + * the doorbell, workqueue and process descriptor, additionally it stores + * information about all possible HW contexts that use it (64 x number of + * engine classes of guc_execlist_context structs). + * + * The idea is that every direct-submission GuC client gets one SW Context ID + * and every HW context created by that client gets one SW Counter. The "SW + * Context ID" and "SW Counter" to use now get passed on every work queue item. + * + * But we don't have direct submission yet: does that mean we are limited to 64 + * contexts in total (one client)? Not really: for non-direct submissions we can + * reserve one or more descriptors to act as "proxy", which are descriptors that + * own a doorbell and a workqueue but contain no HW contexts information. Proxy + * descriptors can be used to submit HW contexts whose info is stored in other + * context descriptors, which we call "principals". With this mechanism, we can + * use almost all descriptors as principals to store HW context info, thus + * increasing the maximum number of contexts we can have. This is a + * generalization of the old proxy submission. * * The Scratch registers: * There are 16 MMIO-based registers start from 0xC180. The kernel driver writes @@ -170,11 +178,28 @@ static int __guc_deallocate_doorbell(struct intel_guc *guc, u32 stage_id) return intel_guc_send(guc, action, ARRAY_SIZE(action)); } -static struct guc_stage_desc *__get_stage_desc(struct intel_guc_client *client) +static struct guc_stage_desc *__get_stage_desc(struct intel_guc *guc, u32 index) +{ + struct guc_stage_desc *base = guc->stage_desc_pool_vaddr; + + GEM_BUG_ON(!USES_GUC_SUBMISSION(guc_to_i915(guc))); + GEM_BUG_ON(index >= GUC_MAX_STAGE_DESCRIPTORS); + + return &base[index]; +} + +static struct guc_stage_desc *__get_proxy_stage_desc(struct intel_guc_client *client) { - struct guc_stage_desc *base = client->guc->stage_desc_pool_vaddr; + GEM_BUG_ON(!I915_SELFTEST_ONLY(client->guc->starting_proxy_id) && + client->stage_id < GUC_MAX_PPAL_STAGE_DESCRIPTORS); + return __get_stage_desc(client->guc, client->stage_id); +} - return &base[client->stage_id]; +static struct guc_stage_desc *__get_ppal_stage_desc(struct intel_guc *guc, + u32 index) +{ + GEM_BUG_ON(index >= GUC_MAX_PPAL_STAGE_DESCRIPTORS); + return __get_stage_desc(guc, index); } /* @@ -189,7 +214,7 @@ static void __update_doorbell_desc(struct intel_guc_client *client, u16 new_id) struct guc_stage_desc *desc; /* Update the GuC's idea of the doorbell ID */ - desc = __get_stage_desc(client); + desc = __get_proxy_stage_desc(client); desc->db_id = new_id; } @@ -342,14 +367,12 @@ static int guc_stage_desc_pool_create(struct intel_guc *guc) guc->stage_desc_pool = vma; guc->stage_desc_pool_vaddr = vaddr; - ida_init(&guc->stage_ids); return 0; } static void guc_stage_desc_pool_destroy(struct intel_guc *guc) { - ida_destroy(&guc->stage_ids); i915_vma_unpin_and_release(&guc->stage_desc_pool, I915_VMA_RELEASE_MAP); } @@ -360,78 +383,26 @@ static void guc_stage_desc_pool_destroy(struct intel_guc *guc) * data structures relating to this client (doorbell, process descriptor, * write queue, etc). */ -static void guc_stage_desc_init(struct intel_guc_client *client) +static void guc_proxy_stage_desc_init(struct intel_guc_client *client) { - struct intel_guc *guc = client->guc; - struct drm_i915_private *dev_priv = guc_to_i915(guc); - struct intel_engine_cs *engine; - struct i915_gem_context *ctx = client->owner; struct guc_stage_desc *desc; - unsigned int tmp; u32 gfx_addr; - desc = __get_stage_desc(client); + desc = __get_proxy_stage_desc(client); memset(desc, 0, sizeof(*desc)); desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE | + GUC_STAGE_DESC_ATTR_PROXY | GUC_STAGE_DESC_ATTR_KERNEL; - if (is_high_priority(client)) - desc->attribute |= GUC_STAGE_DESC_ATTR_PREEMPT; desc->stage_id = client->stage_id; desc->priority = client->priority; desc->db_id = client->doorbell_id; - for_each_engine_masked(engine, dev_priv, client->engines, tmp) { - struct intel_context *ce = intel_context_lookup(ctx, engine); - u32 guc_engine_id = engine->guc_id; - struct guc_execlist_context *lrc = &desc->lrc[guc_engine_id]; - - /* TODO: We have a design issue to be solved here. Only when we - * receive the first batch, we know which engine is used by the - * user. But here GuC expects the lrc and ring to be pinned. It - * is not an issue for default context, which is the only one - * for now who owns a GuC client. But for future owner of GuC - * client, need to make sure lrc is pinned prior to enter here. - */ - if (!ce || !ce->state) - break; /* XXX: continue? */ - - /* - * XXX: When this is a GUC_STAGE_DESC_ATTR_KERNEL client (proxy - * submission or, in other words, not using a direct submission - * model) the KMD's LRCA is not used for any work submission. - * Instead, the GuC uses the LRCA of the user mode context (see - * guc_add_request below). - */ - lrc->context_desc = lower_32_bits(ce->lrc_desc); - - /* The state page is after PPHWSP */ - lrc->ring_lrca = intel_guc_ggtt_offset(guc, ce->state) + - LRC_STATE_PN * PAGE_SIZE; - - /* XXX: In direct submission, the GuC wants the HW context id - * here. In proxy submission, it wants the stage id - */ - lrc->context_id = (client->stage_id << GUC_ELC_CTXID_OFFSET) | - (guc_engine_id << GUC_ELC_ENGINE_OFFSET); - - lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma); - lrc->ring_end = lrc->ring_begin + ce->ring->size - 1; - lrc->ring_next_free_location = lrc->ring_begin; - lrc->ring_current_tail_pointer_value = 0; - - desc->engines_used |= (1 << guc_engine_id); - } - - DRM_DEBUG_DRIVER("Host engines 0x%x => GuC engines used 0x%x\n", - client->engines, desc->engines_used); - WARN_ON(desc->engines_used == 0); - /* * The doorbell, process descriptor, and workqueue are all parts * of the client object, which the GuC will reference via the GGTT */ - gfx_addr = intel_guc_ggtt_offset(guc, client->vma); + gfx_addr = intel_guc_ggtt_offset(client->guc, client->vma); desc->db_trigger_phy = sg_dma_address(client->vma->pages->sgl) + client->doorbell_offset; desc->db_trigger_cpu = ptr_to_u64(__get_doorbell(client)); @@ -443,11 +414,11 @@ static void guc_stage_desc_init(struct intel_guc_client *client) desc->desc_private = ptr_to_u64(client); } -static void guc_stage_desc_fini(struct intel_guc_client *client) +static void guc_proxy_stage_desc_fini(struct intel_guc_client *client) { struct guc_stage_desc *desc; - desc = __get_stage_desc(client); + desc = __get_proxy_stage_desc(client); memset(desc, 0, sizeof(*desc)); } @@ -566,7 +537,7 @@ static void inject_preempt_context(struct work_struct *work) struct intel_guc *guc = container_of(preempt_work, typeof(*guc), preempt_work[engine->id]); struct intel_guc_client *client = guc->preempt_client; - struct guc_stage_desc *stage_desc = __get_stage_desc(client); + struct guc_stage_desc *stage_desc = __get_proxy_stage_desc(client); struct intel_context *ce = intel_context_lookup(client->owner, engine); u32 data[7]; @@ -931,6 +902,7 @@ guc_client_alloc(struct drm_i915_private *dev_priv, struct i915_vma *vma; void *vaddr; int ret; + u32 starting_id = GUC_MAX_PPAL_STAGE_DESCRIPTORS; client = kzalloc(sizeof(*client), GFP_KERNEL); if (!client) @@ -943,8 +915,13 @@ guc_client_alloc(struct drm_i915_private *dev_priv, client->doorbell_id = GUC_DOORBELL_INVALID; spin_lock_init(&client->wq_lock); - ret = ida_simple_get(&guc->stage_ids, 0, GUC_MAX_STAGE_DESCRIPTORS, - GFP_KERNEL); +#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) + if (unlikely(guc->starting_proxy_id)) + starting_id = guc->starting_proxy_id; +#endif + + ret = ida_simple_get(&guc->client_ids, starting_id, + GUC_MAX_STAGE_DESCRIPTORS, GFP_KERNEL); if (ret < 0) goto err_client; @@ -995,7 +972,7 @@ guc_client_alloc(struct drm_i915_private *dev_priv, err_vma: i915_vma_unpin_and_release(&client->vma, 0); err_id: - ida_simple_remove(&guc->stage_ids, client->stage_id); + ida_simple_remove(&guc->client_ids, client->stage_id); err_client: kfree(client); return ERR_PTR(ret); @@ -1005,7 +982,7 @@ static void guc_client_free(struct intel_guc_client *client) { unreserve_doorbell(client); i915_vma_unpin_and_release(&client->vma, I915_VMA_RELEASE_MAP); - ida_simple_remove(&client->guc->stage_ids, client->stage_id); + ida_simple_remove(&client->guc->client_ids, client->stage_id); kfree(client); } @@ -1075,7 +1052,7 @@ static int __guc_client_enable(struct intel_guc_client *client) int ret; guc_proc_desc_init(client); - guc_stage_desc_init(client); + guc_proxy_stage_desc_init(client); ret = create_doorbell(client); if (ret) @@ -1084,7 +1061,7 @@ static int __guc_client_enable(struct intel_guc_client *client) return 0; fail: - guc_stage_desc_fini(client); + guc_proxy_stage_desc_fini(client); guc_proc_desc_fini(client); return ret; } @@ -1101,7 +1078,7 @@ static void __guc_client_disable(struct intel_guc_client *client) else __fini_doorbell(client); - guc_stage_desc_fini(client); + guc_proxy_stage_desc_fini(client); guc_proc_desc_fini(client); } @@ -1157,6 +1134,9 @@ int intel_guc_submission_init(struct intel_guc *guc) GEM_BUG_ON(!guc->stage_desc_pool); WARN_ON(!guc_verify_doorbells(guc)); + + ida_init(&guc->client_ids); + ret = guc_clients_create(guc); if (ret) goto err_pool; @@ -1169,6 +1149,7 @@ int intel_guc_submission_init(struct intel_guc *guc) return 0; err_pool: + ida_destroy(&guc->client_ids); guc_stage_desc_pool_destroy(guc); return ret; } @@ -1185,6 +1166,8 @@ void intel_guc_submission_fini(struct intel_guc *guc) guc_clients_destroy(guc); WARN_ON(!guc_verify_doorbells(guc)); + ida_destroy(&guc->client_ids); + if (guc->stage_desc_pool) guc_stage_desc_pool_destroy(guc); } @@ -1269,6 +1252,197 @@ static void guc_submission_unpark(struct intel_engine_cs *engine) intel_engine_pin_breadcrumbs_irq(engine); } +static void guc_map_gem_ctx_to_ppal_stage(struct intel_guc *guc, + struct guc_stage_desc *desc, + u32 id) +{ + GEM_BUG_ON(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE); + + desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE | + GUC_STAGE_DESC_ATTR_PRINCIPAL | + GUC_STAGE_DESC_ATTR_KERNEL; + desc->stage_id = id; + + /* all ppal contexts will be submitted trough the execbuf client */ + desc->proxy_id = guc->execbuf_client->stage_id; + + /* + * max_lrc_per_class is used in GuC to cut short loops over the + * lrc_bitmap when only a small amount of lrcs are used. We could + * recalculate this value every time an lrc is added or removed, but + * given the fact that we only have a max number of lrcs per stage_desc + * equal to the max number of instances of a class (because we map + * gem_context 1:1 with stage_desc) and that the GuC loops only in + * specific cases, redoing the calculation each time doesn't give us a + * big benefit for the cost so we can just use a static value. + */ + desc->max_lrc_per_class = MAX_ENGINE_INSTANCE + 1; +} + +static void guc_unmap_gem_ctx_from_ppal_stage(struct intel_guc *guc, + struct guc_stage_desc *desc) +{ + GEM_BUG_ON(!(desc->attribute & GUC_STAGE_DESC_ATTR_ACTIVE)); + GEM_BUG_ON(desc->lrc_count > 0); + + memset(desc, 0, sizeof(*desc)); +} + +static inline void guc_ppal_stage_lrc_pin(struct intel_context *ce) +{ + struct intel_engine_cs *engine = ce->engine; + struct intel_guc *guc = &engine->i915->guc; + struct guc_stage_desc *desc; + struct guc_execlist_context *lrc; + u8 guc_class = engine->class; + + /* 1:1 gem_context to ppal mapping */ + GEM_BUG_ON(ce->sw_counter > MAX_ENGINE_INSTANCE); + + desc = __get_ppal_stage_desc(guc, ce->sw_context_id); + GEM_BUG_ON(desc->lrc_alloc_map[guc_class].bitmap & + BIT_ULL(ce->sw_counter)); + + if (!desc->lrc_count++) + guc_map_gem_ctx_to_ppal_stage(guc, desc, ce->sw_context_id); + + lrc = &desc->lrc[guc_class][ce->sw_counter]; + lrc->hw_context_desc = ce->lrc_desc; + lrc->ring_lrc = intel_guc_ggtt_offset(guc, ce->state) + + LRC_STATE_PN * PAGE_SIZE; + lrc->ring_begin = intel_guc_ggtt_offset(guc, ce->ring->vma); + lrc->ring_end = lrc->ring_begin + ce->ring->size - 1; + + desc->lrc_alloc_map[guc_class].bitmap |= BIT_ULL(ce->sw_counter); +} + +static inline void guc_ppal_stage_lrc_unpin(struct intel_context *ce) +{ + struct i915_gem_context *ctx = ce->gem_context; + struct intel_guc *guc = &ctx->i915->guc; + struct intel_engine_cs *engine = ce->engine; + struct guc_stage_desc *desc; + struct guc_execlist_context *lrc; + u8 guc_class = engine->class; + + desc = __get_ppal_stage_desc(guc, ce->sw_context_id); + GEM_BUG_ON(!(desc->lrc_alloc_map[guc_class].bitmap & + BIT_ULL(ce->sw_counter))); + + lrc = &desc->lrc[guc_class][ce->sw_counter]; + + /* + * GuC needs us to keep the lrc mapped until it has finished processing + * the ctx switch interrupt. When executing nop or very small workloads + * it is possible (but quite unlikely) that 2 contexts on different + * ELSPs of the same engine complete before the GuC manages to process + * the interrupt for the first completion. Experiments show this happens + * for ~0.2% of contexts when executing nop workloads on different + * contexts back to back on the same engine. When submitting nop + * workloads on all engines at the same time the hit-rate goes up to + * ~0.7%. In all the observed cases GuC required < 100us to catch up, + * with the single engine case being always below 20us. + * + * The completion of the request on the second lrc will reduce our + * pin_count on the first lrc to zero, thus triggering a call to this + * function potentially before GuC has had time to process the + * interrupt. To avoid this, we could get an extra pin on the context or + * delay the unpin when guc is in use, but given that the issue is + * limited to pathological scenarios and has very low hit rate even + * there, we can just introduce a small delay when it happens to give + * time to GuC to catch up. Also to be noted that since the requests + * have completed on the HW we've most likely already sent GuC the next + * contexts to be executed, so it is unlikely that by waiting we'll add + * bubbles in the HW execution. + */ + if (likely(intel_guc_is_alive(guc))) + WARN_ON(wait_for_us(lrc->is_present_in_sq == 0, 1000)); + + desc->lrc_alloc_map[guc_class].bitmap &= ~BIT_ULL(ce->sw_counter); + memset(lrc, 0, sizeof(*lrc)); + + if (!--desc->lrc_count) + guc_unmap_gem_ctx_from_ppal_stage(guc, desc); +} + +static inline void guc_init_lrc_mapping(struct intel_guc *guc) +{ + struct drm_i915_private *i915 = guc_to_i915(guc); + struct intel_engine_cs *engine; + struct i915_gem_context *ctx; + struct intel_context *ce; + enum intel_engine_id id; + + /* + * Some contexts (e.g. kernel_context) might have been pinned before we + * enabled GuC submission, so we need to add them to the GuC bookeping. + * Also, after a reset the GuC we want to make sure that the information + * shared with GuC is properly reset. + * + * NOTE: the code below assumes 1:1 mapping between ppal descriptors and + * gem contexts for simplicity. + */ + list_for_each_entry(ctx, &i915->contexts.list, link) { + if (atomic_read(&ctx->hw_id_pin_count)) { + struct guc_stage_desc *desc; + + /* make sure the descriptor is clean... */ + GEM_BUG_ON(ctx->hw_id > GUC_MAX_PPAL_STAGE_DESCRIPTORS); + desc = __get_ppal_stage_desc(guc, ctx->hw_id); + memset(desc, 0, sizeof(*desc)); + + /* ...and the (re-)pin all the lrcs */ + for_each_engine(engine, i915, id) { + ce = intel_context_lookup(ctx, engine); + if (ce && intel_context_is_pinned(ce)) + guc_ppal_stage_lrc_pin(ce); + } + } + } +} + +static inline void guc_fini_lrc_mapping(struct intel_guc *guc) +{ + struct drm_i915_private *i915 = guc_to_i915(guc); + struct intel_engine_cs *engine; + struct i915_gem_context *ctx; + struct intel_context *ce; + enum intel_engine_id id; + + list_for_each_entry(ctx, &i915->contexts.list, link) { + if (atomic_read(&ctx->hw_id_pin_count)) { + for_each_engine(engine, i915, id) { + ce = intel_context_lookup(ctx, engine); + if (ce && intel_context_is_pinned(ce)) + guc_ppal_stage_lrc_unpin(ce); + } + } + } +} + +static void guc_context_unpin(struct intel_context *ce) +{ + guc_ppal_stage_lrc_unpin(ce); + intel_execlists_context_unpin(ce); +} + +static int guc_context_pin(struct intel_context *ce) +{ + int ret = 0; + + ret = intel_execlists_context_pin(ce); + if (!ret) + guc_ppal_stage_lrc_pin(ce); + + return ret; +} + +static const struct intel_context_ops guc_context_ops = { + .pin = guc_context_pin, + .unpin = guc_context_unpin, + .destroy = intel_execlists_context_destroy, +}; + static void guc_set_default_submission(struct intel_engine_cs *engine) { /* @@ -1286,6 +1460,8 @@ static void guc_set_default_submission(struct intel_engine_cs *engine) engine->execlists.tasklet.func = guc_submission_tasklet; + engine->cops = &guc_context_ops; + engine->park = guc_submission_park; engine->unpark = guc_submission_unpark; @@ -1328,6 +1504,8 @@ int intel_guc_submission_enable(struct intel_guc *guc) engine->set_default_submission(engine); } + guc_init_lrc_mapping(guc); + return 0; } @@ -1337,6 +1515,7 @@ void intel_guc_submission_disable(struct intel_guc *guc) GEM_BUG_ON(dev_priv->gt.awake); /* GT should be parked first */ + guc_fini_lrc_mapping(guc); guc_interrupts_release(dev_priv); guc_clients_disable(guc); } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 31db38560680..e750ff31e58e 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1237,7 +1237,7 @@ static void __execlists_context_fini(struct intel_context *ce) i915_gem_object_put(ce->state->obj); } -static void execlists_context_destroy(struct kref *kref) +void intel_execlists_context_destroy(struct kref *kref) { struct intel_context *ce = container_of(kref, typeof(*ce), ref); @@ -1273,7 +1273,7 @@ static void __context_unpin(struct i915_vma *vma) __i915_vma_unpin(vma); } -static void execlists_context_unpin(struct intel_context *ce) +void intel_execlists_context_unpin(struct intel_context *ce) { struct intel_engine_cs *engine; @@ -1380,15 +1380,15 @@ __execlists_context_pin(struct intel_context *ce, return ret; } -static int execlists_context_pin(struct intel_context *ce) +int intel_execlists_context_pin(struct intel_context *ce) { return __execlists_context_pin(ce, ce->engine); } static const struct intel_context_ops execlists_context_ops = { - .pin = execlists_context_pin, - .unpin = execlists_context_unpin, - .destroy = execlists_context_destroy, + .pin = intel_execlists_context_pin, + .unpin = intel_execlists_context_unpin, + .destroy = intel_execlists_context_destroy, }; static int gen8_emit_init_breadcrumb(struct i915_request *rq) diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index 92642ab91472..addf796355de 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -114,4 +114,8 @@ void intel_execlists_show_requests(struct intel_engine_cs *engine, u32 gen8_make_rpcs(struct drm_i915_private *i915, struct intel_sseu *ctx_sseu); +int intel_execlists_context_pin(struct intel_context *ce); +void intel_execlists_context_unpin(struct intel_context *ce); +void intel_execlists_context_destroy(struct kref *kref); + #endif /* _INTEL_LRC_H_ */ diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/selftests/intel_guc.c index b05a21eaa8f4..0102ee90355c 100644 --- a/drivers/gpu/drm/i915/selftests/intel_guc.c +++ b/drivers/gpu/drm/i915/selftests/intel_guc.c @@ -259,6 +259,8 @@ static int igt_guc_doorbells(void *arg) if (err) goto unlock; + BUILD_BUG_ON(GUC_MAX_PPAL_STAGE_DESCRIPTORS < ATTEMPTS); + guc->starting_proxy_id = GUC_MAX_PPAL_STAGE_DESCRIPTORS - ATTEMPTS; for (i = 0; i < ATTEMPTS; i++) { clients[i] = guc_client_alloc(dev_priv, INTEL_INFO(dev_priv)->engine_mask, @@ -288,11 +290,19 @@ static int igt_guc_doorbells(void *arg) continue; } + if (clients[i]->stage_id < guc->starting_proxy_id) { + pr_err("[%u] invalid stage id %u assigned to client\n", + i, clients[i]->stage_id); + err = -EINVAL; + goto out; + } + /* * The check below is only valid because we keep a doorbell * assigned during the whole life of the client. */ - if (clients[i]->stage_id >= GUC_NUM_DOORBELLS) { + if ((clients[i]->stage_id - guc->starting_proxy_id) >= + GUC_NUM_DOORBELLS) { pr_err("[%d] more clients than doorbells (%d >= %d)\n", i, clients[i]->stage_id, GUC_NUM_DOORBELLS); err = -EINVAL; @@ -338,6 +348,8 @@ static int igt_guc_doorbells(void *arg) __guc_client_disable(clients[i]); guc_client_free(clients[i]); } + + guc->starting_proxy_id = 0; unlock: intel_runtime_pm_put(dev_priv, wakeref); mutex_unlock(&dev_priv->drm.struct_mutex); From patchwork Fri Mar 29 22:11:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877843 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0F57617E0 for ; Fri, 29 Mar 2019 22:12:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EE8FC2906F for ; Fri, 29 Mar 2019 22:12:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E1408292B4; Fri, 29 Mar 2019 22:12:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 67BA22906F for ; Fri, 29 Mar 2019 22:12:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5F0556E569; Fri, 29 Mar 2019 22:12:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id ED2A36E569 for ; Fri, 29 Mar 2019 22:11:48 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="156522334" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga002.fm.intel.com with ESMTP; 29 Mar 2019 15:11:46 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0m017079; Fri, 29 Mar 2019 22:11:44 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:10 +0000 Message-Id: <20190329221118.17308-23-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 22/30] drm/i915/guc: New GuC workqueue item submission mechanism X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Work queue items definitions were updated. To simplify the scheduling logic in the GuC firmware, only out-of-order mode of scheduling is now supported. Credits-to: Michel Thierry Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen Cc: Tvrtko Ursulin Cc: Michał Winiarski Cc: Tomasz Lis --- drivers/gpu/drm/i915/intel_guc_fwif.h | 18 +++++++++---- drivers/gpu/drm/i915/intel_guc_submission.c | 29 ++++++++++++++------- drivers/gpu/drm/i915/selftests/intel_guc.c | 2 +- 3 files changed, 34 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index a900680ff5a4..004d3d882f6f 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -49,22 +49,30 @@ #define GUC_DB_SIZE (PAGE_SIZE) #define GUC_WQ_SIZE (PAGE_SIZE * 2) -/* Work queue item header definitions */ +/* Work queue status */ #define WQ_STATUS_ACTIVE 1 #define WQ_STATUS_SUSPENDED 2 #define WQ_STATUS_CMD_ERROR 3 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 +#define WQ_STATUS_INVALID 6 + +/* Work queue item header definitions */ #define WQ_TYPE_SHIFT 0 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) -#define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) +#define WQ_TYPE_KMD (0x3 << WQ_TYPE_SHIFT) #define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT) -#define WQ_TARGET_SHIFT 10 +#define WQ_TYPE_RESUME (0x5 << WQ_TYPE_SHIFT) +#define WQ_TYPE_INVALID (0x6 << WQ_TYPE_SHIFT) +#define WQ_TARGET_SHIFT 8 #define WQ_LEN_SHIFT 16 -#define WQ_NO_WCFLUSH_WAIT (1 << 27) -#define WQ_PRESENT_WORKLOAD (1 << 28) +#define WQ_LEN_MASK (0x7FF << WQ_LEN_SHIFT) +/* Work queue item submit element info definitions */ +#define WQ_SW_CTX_INDEX_SHIFT 0 +#define WQ_SW_COUNTER_SHIFT 11 +#define WQ_RING_TAIL_INDEX_SHIFT 18 #define WQ_RING_TAIL_SHIFT 20 #define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */ #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index 3104f091abc5..1a27352b73a9 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -82,9 +82,14 @@ * Work Items: * There are several types of work items that the host may place into a * workqueue, each with its own requirements and limitations. Currently only - * WQ_TYPE_INORDER is needed to support legacy submission via GuC, which - * represents in-order queue. The kernel driver packs ring tail pointer and an - * ELSP context descriptor dword into Work Item. + * out-of-order WQ_TYPE_KMD is supported by the firmware. + * Our in-orderness is guaranteed by the execlists emulation with two "fake" + * ports that the scheduler uses when submitting to the GuC backend. If we are + * submitting requests for context A in the first port and we place a request + * for context B in the second port, we won't submit more requests for A until + * all the pending ones complete. We have to take this into account if we try + * to change the current execlist emulation model (e.g.: increasing the number + * of fake ports could cause requests to execute in wrong global seqno order). * See guc_add_request() * */ @@ -424,6 +429,7 @@ static void guc_proxy_stage_desc_fini(struct intel_guc_client *client) /* Construct a Work Item and append it to the GuC's Work Queue */ static void guc_wq_item_append(struct intel_guc_client *client, + struct intel_context *ce, u32 target_engine, u32 context_desc, u32 ring_tail, u32 fence_id) { @@ -461,12 +467,15 @@ static void guc_wq_item_append(struct intel_guc_client *client, wqi->header = WQ_TYPE_NOOP | (wqi_len << WQ_LEN_SHIFT); } else { /* Now fill in the 4-word work queue item */ - wqi->header = WQ_TYPE_INORDER | - (wqi_len << WQ_LEN_SHIFT) | + wqi->header = WQ_TYPE_KMD | (target_engine << WQ_TARGET_SHIFT) | - WQ_NO_WCFLUSH_WAIT; + (wqi_len << WQ_LEN_SHIFT); wqi->context_desc = context_desc; - wqi->submit_element_info = ring_tail << WQ_RING_TAIL_SHIFT; + + wqi->submit_element_info = + (ce->sw_context_id << WQ_SW_CTX_INDEX_SHIFT) | + (ce->sw_counter << WQ_SW_COUNTER_SHIFT | + (ring_tail << WQ_RING_TAIL_INDEX_SHIFT)); GEM_BUG_ON(ring_tail > WQ_RING_TAIL_MAX); wqi->fence_id = fence_id; } @@ -500,12 +509,13 @@ static void guc_add_request(struct intel_guc *guc, struct i915_request *rq) { struct intel_guc_client *client = guc->execbuf_client; struct intel_engine_cs *engine = rq->engine; + struct intel_context *ce = rq->hw_context; u32 ctx_desc = lower_32_bits(rq->hw_context->lrc_desc); u32 ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64); spin_lock(&client->wq_lock); - guc_wq_item_append(client, engine->guc_id, ctx_desc, + guc_wq_item_append(client, ce, engine->guc_id, ctx_desc, ring_tail, rq->fence.seqno); guc_ring_doorbell(client); @@ -569,7 +579,8 @@ static void inject_preempt_context(struct work_struct *work) } spin_lock_irq(&client->wq_lock); - guc_wq_item_append(client, engine->guc_id, lower_32_bits(ce->lrc_desc), + guc_wq_item_append(client, ce, engine->guc_id, + lower_32_bits(ce->lrc_desc), GUC_PREEMPT_BREADCRUMB_BYTES / sizeof(u64), 0); spin_unlock_irq(&client->wq_lock); diff --git a/drivers/gpu/drm/i915/selftests/intel_guc.c b/drivers/gpu/drm/i915/selftests/intel_guc.c index 0102ee90355c..4f9adb2dccda 100644 --- a/drivers/gpu/drm/i915/selftests/intel_guc.c +++ b/drivers/gpu/drm/i915/selftests/intel_guc.c @@ -74,7 +74,7 @@ static int ring_doorbell_nop(struct intel_guc_client *client) spin_lock_irq(&client->wq_lock); - guc_wq_item_append(client, 0, 0, 0, 0); + guc_wq_item_append(client, NULL, 0, 0, 0, 0); guc_ring_doorbell(client); spin_unlock_irq(&client->wq_lock); From patchwork Fri Mar 29 22:11:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877849 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 10C63186D for ; Fri, 29 Mar 2019 22:12:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F0BAE28E8F for ; Fri, 29 Mar 2019 22:12:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E5576292AE; Fri, 29 Mar 2019 22:12:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 711A62906F for ; Fri, 29 Mar 2019 22:12:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9EE536E572; Fri, 29 Mar 2019 22:12:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id BDC1C6E56C for ; Fri, 29 Mar 2019 22:11:48 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="333327861" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga005.fm.intel.com with ESMTP; 29 Mar 2019 15:11:47 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0n017079; Fri, 29 Mar 2019 22:11:45 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:11 +0000 Message-Id: <20190329221118.17308-24-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 23/30] drm/i915/guc: Add support for resume-parsing wq item X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michel Thierry MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Since fw version 25.161, GuC lets us know when an engine had to be reset due to a hang in another dependent engine, by setting BIT(engine_class) in the queue_engine_error field. GuC will ignore any other wq item until this flag is cleared. To restart the workqueue processing for that engine, we must insert a special wq item called resume-parsing and wait until the queue_engine_error field is updated. Co-Developed-by: Michel Thierry Co-Developed-by: Michal Wajdeczko Signed-off-by: Michel Thierry Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Vinay Belgaumkar Cc: Michal Winiarski Cc: Tomasz Lis --- drivers/gpu/drm/i915/intel_guc_submission.c | 92 +++++++++++++++++++-- 1 file changed, 86 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index 1a27352b73a9..b0b10cac9b9b 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -427,6 +427,76 @@ static void guc_proxy_stage_desc_fini(struct intel_guc_client *client) memset(desc, 0, sizeof(*desc)); } +static u32 get_wq_offset(struct guc_process_desc *desc) +{ + const size_t wqi_size = sizeof(struct guc_wq_item); + u32 wq_off; + + /* + * Free space is guaranteed, either by normal port submission or + * because we waited for the wq_resume to be processed. + */ + wq_off = READ_ONCE(desc->tail); + GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head), + GUC_WQ_SIZE) < wqi_size); + GEM_BUG_ON(wq_off & (wqi_size - 1)); + + return wq_off; +} + +static void write_wqi(struct guc_process_desc *desc, u32 wq_off) +{ + const size_t wqi_size = sizeof(struct guc_wq_item); + + WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1)); +} + +static void guc_append_wq_resume_parsing_item(struct intel_guc_client *client, + struct intel_engine_cs *engine) +{ + struct guc_process_desc *desc = __get_process_desc(client); + const u32 target_engine = engine->guc_id; + const u32 wqi_resume = WQ_TYPE_RESUME | + (target_engine << WQ_TARGET_SHIFT) | + (0 << WQ_LEN_SHIFT); + const u32 wqi_noop = WQ_TYPE_NOOP | + (target_engine << WQ_TARGET_SHIFT) | + (0 << WQ_LEN_SHIFT); + struct guc_wq_item *wqi; + u32 wq_off; + + lockdep_assert_held(&client->wq_lock); + + wq_off = get_wq_offset(desc); + wqi = client->vaddr + wq_off + GUC_DB_SIZE; + + /* + * Submit 4 wq_items (1 RESUME_WQ_PARSING followed by 3 NOOPs) in + * order to keep it the same size as a 'normal' wq_item. + */ + wqi->header = wqi_resume; + wqi->context_desc = wqi_noop; + wqi->submit_element_info = wqi_noop; + wqi->fence_id = wqi_noop; + + write_wqi(desc, wq_off); +} + +#define GUC_WAIT_FOR_ENGINE_ERROR_CLEANED_MS 10 + +static void guc_wait_wq_resumed(struct intel_guc_client *client, + struct intel_engine_cs *engine) +{ + struct guc_process_desc *desc = __get_process_desc(client); + u8 guc_class = engine->class; + + lockdep_assert_held(&client->wq_lock); + + /* must wait for the flag to be cleared */ + WARN_ON(wait_for_atomic(!(desc->queue_engine_error & BIT(guc_class)), + GUC_WAIT_FOR_ENGINE_ERROR_CLEANED_MS)); +} + /* Construct a Work Item and append it to the GuC's Work Queue */ static void guc_wq_item_append(struct intel_guc_client *client, struct intel_context *ce, @@ -454,11 +524,7 @@ static void guc_wq_item_append(struct intel_guc_client *client, /* We expect the WQ to be active if we're appending items to it */ GEM_BUG_ON(desc->wq_status != WQ_STATUS_ACTIVE); - /* Free space is guaranteed. */ - wq_off = READ_ONCE(desc->tail); - GEM_BUG_ON(CIRC_SPACE(wq_off, READ_ONCE(desc->head), - GUC_WQ_SIZE) < wqi_size); - GEM_BUG_ON(wq_off & (wqi_size - 1)); + wq_off = get_wq_offset(desc); /* WQ starts from the page after doorbell / process_desc */ wqi = client->vaddr + wq_off + GUC_DB_SIZE; @@ -481,7 +547,7 @@ static void guc_wq_item_append(struct intel_guc_client *client, } /* Make the update visible to GuC */ - WRITE_ONCE(desc->tail, (wq_off + wqi_size) & (GUC_WQ_SIZE - 1)); + write_wqi(desc, wq_off); } static void guc_ring_doorbell(struct intel_guc_client *client) @@ -505,6 +571,14 @@ static void guc_ring_doorbell(struct intel_guc_client *client) GEM_BUG_ON(db->db_status != GUC_DOORBELL_ENABLED); } +static bool guc_needs_wq_resume_parsing_item(struct intel_guc_client *client, + u32 target_engine_class) +{ + struct guc_process_desc *desc = __get_process_desc(client); + + return desc->queue_engine_error & BIT(target_engine_class); +} + static void guc_add_request(struct intel_guc *guc, struct i915_request *rq) { struct intel_guc_client *client = guc->execbuf_client; @@ -512,9 +586,15 @@ static void guc_add_request(struct intel_guc *guc, struct i915_request *rq) struct intel_context *ce = rq->hw_context; u32 ctx_desc = lower_32_bits(rq->hw_context->lrc_desc); u32 ring_tail = intel_ring_set_tail(rq->ring, rq->tail) / sizeof(u64); + u8 guc_class = engine->class; spin_lock(&client->wq_lock); + if (guc_needs_wq_resume_parsing_item(client, guc_class)) { + guc_append_wq_resume_parsing_item(client, engine); + guc_wait_wq_resumed(client, engine); + } + guc_wq_item_append(client, ce, engine->guc_id, ctx_desc, ring_tail, rq->fence.seqno); guc_ring_doorbell(client); From patchwork Fri Mar 29 22:11:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877855 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 430AC186D for ; Fri, 29 Mar 2019 22:12:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2F9DF28E8F for ; Fri, 29 Mar 2019 22:12:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2433C292AE; Fri, 29 Mar 2019 22:12:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B94BB28E8F for ; Fri, 29 Mar 2019 22:12:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C4836E577; Fri, 29 Mar 2019 22:12:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 280396E56E for ; Fri, 29 Mar 2019 22:11:50 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="156522344" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga002.fm.intel.com with ESMTP; 29 Mar 2019 15:11:48 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0o017079; Fri, 29 Mar 2019 22:11:46 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:12 +0000 Message-Id: <20190329221118.17308-25-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 24/30] drm/i915/guc: New reset-engine command X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michel Thierry MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Format of the ENGINE_RESET H2G message has been updated. Additionally, the firmware will send a G2H ENGINE_RESET_COMPLETE message (with the engine's guc_class in data[2]) to confirm that the reset has been completed (but this will be handled in a other patch). Co-Developed-by: Michel Thierry Signed-off-by: Michel Thierry Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Vinay Belgaumkar Cc: Michal Winiarski Cc: Tomasz Lis --- drivers/gpu/drm/i915/intel_guc.c | 73 +++++++++++++++++++++++++++----- drivers/gpu/drm/i915/intel_guc.h | 6 +++ 2 files changed, 69 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index e54de551b567..abedb8982040 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -610,27 +610,80 @@ int intel_guc_suspend(struct intel_guc *guc) return guc_sleep_state_action(guc, data, ARRAY_SIZE(data)); } +static inline void +guc_set_class_under_reset(struct intel_guc *guc, unsigned int guc_class) +{ + GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES); + guc->engine_class_under_reset |= BIT(guc_class); +} + +static inline void +guc_clear_class_under_reset(struct intel_guc *guc, unsigned int guc_class) +{ + GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES); + guc->engine_class_under_reset &= ~BIT(guc_class); +} + +static inline bool +guc_is_class_under_reset(struct intel_guc *guc, unsigned int guc_class) +{ + return guc->engine_class_under_reset & BIT(guc_class); +} + +static int __guc_action_reset_engine(struct intel_guc *guc, + u32 guc_class, + u32 stage_id) +{ + u32 action[] = { + INTEL_GUC_ACTION_REQUEST_ENGINE_RESET, + guc_class, + stage_id, + }; + + return intel_guc_send(guc, action, ARRAY_SIZE(action)); +} + +#define GUC_ENGINE_RESET_COMPLETE_WAIT_MS 100 + /** * intel_guc_reset_engine() - ask GuC to reset an engine * @guc: intel_guc structure * @engine: engine to be reset + * + * Ask GuC to reset an engine. The firmware will send a separate + * ENGINE_RESET_COMPLETE message (with the engine's guc_class) + * to confirm that the reset has been completed. */ int intel_guc_reset_engine(struct intel_guc *guc, struct intel_engine_cs *engine) { - u32 data[7]; + struct intel_guc_client *client = guc->execbuf_client; + u8 guc_class = engine->class; + int ret; - GEM_BUG_ON(!guc->execbuf_client); + GEM_BUG_ON(guc_is_class_under_reset(guc, guc_class)); + guc_set_class_under_reset(guc, guc_class); - data[0] = INTEL_GUC_ACTION_REQUEST_ENGINE_RESET; - data[1] = engine->guc_id; - data[2] = 0; - data[3] = 0; - data[4] = 0; - data[5] = guc->execbuf_client->stage_id; - data[6] = intel_guc_ggtt_offset(guc, guc->shared_data); + ret = __guc_action_reset_engine(guc, guc_class, client->stage_id); + if (ret) + goto fail; - return intel_guc_send(guc, data, ARRAY_SIZE(data)); + ret = wait_for(!guc_is_class_under_reset(guc, guc_class), + GUC_ENGINE_RESET_COMPLETE_WAIT_MS); + if (ret) + goto fail_timedout; + + return 0; + +fail_timedout: + DRM_ERROR("reset_complete timed out, engine class %u\n", guc_class); +fail: + /* + * Clear flag on any failure, we fall back to full reset in + * case of timeout/error. + */ + guc_clear_class_under_reset(guc, guc_class); + return ret; } /** diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index dbe4297f8a7d..a4bc3355a753 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -80,6 +80,12 @@ struct intel_guc { /* Cyclic counter mod pagesize */ u32 db_cacheline; + /* + * Track outstanding request-engine-reset h2g commands, + * accessed by set/clear/is_engine_class_under_reset + */ + unsigned long engine_class_under_reset; + /* GuC's FW specific registers used in MMIO send */ struct { u32 base; From patchwork Fri Mar 29 22:11:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877865 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2CDFE17E0 for ; Fri, 29 Mar 2019 22:12:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 192ED28E8F for ; Fri, 29 Mar 2019 22:12:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0DB87292AE; Fri, 29 Mar 2019 22:12:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A458028E8F for ; Fri, 29 Mar 2019 22:12:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 54BEE6E582; Fri, 29 Mar 2019 22:12:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 29BA46E56C for ; Fri, 29 Mar 2019 22:11:51 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="138453074" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga003.jf.intel.com with ESMTP; 29 Mar 2019 15:11:49 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0p017079; Fri, 29 Mar 2019 22:11:48 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:13 +0000 Message-Id: <20190329221118.17308-26-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 25/30] drm/i915/guc: New engine-reset-complete message X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP GuC sends ENGINE_RESET_COMPLETE message as an follow-up answer to earlier ENGINE_RESET request from the host. Once this message is received, clear engine reset flag to unblock our reset process. Credits-to: Michel Thierry Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Vinay Belgaumkar Cc: Michal Winiarski Cc: Tomasz Lis --- drivers/gpu/drm/i915/intel_guc.c | 29 +++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_guc_fwif.h | 3 ++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index abedb8982040..c9fbda2e8a78 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -27,6 +27,9 @@ #include "intel_guc_submission.h" #include "i915_drv.h" +static void guc_handle_engine_reset_completed(struct intel_guc *guc, + const u32 engine_class); + static void gen8_guc_raise_irq(struct intel_guc *guc) { struct drm_i915_private *dev_priv = guc_to_i915(guc); @@ -517,6 +520,12 @@ int intel_guc_to_host_process_recv_msg(struct intel_guc *guc, INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)) intel_guc_log_handle_flush_event(&guc->log); + if (msg & INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE) { + if (len != 3) + return -EPROTO; + guc_handle_engine_reset_completed(guc, payload[1]); + } + return 0; } @@ -615,6 +624,7 @@ guc_set_class_under_reset(struct intel_guc *guc, unsigned int guc_class) { GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES); guc->engine_class_under_reset |= BIT(guc_class); + intel_guc_enable_msg(guc, INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE); } static inline void @@ -622,6 +632,7 @@ guc_clear_class_under_reset(struct intel_guc *guc, unsigned int guc_class) { GEM_BUG_ON(guc_class >= GUC_MAX_ENGINE_CLASSES); guc->engine_class_under_reset &= ~BIT(guc_class); + intel_guc_disable_msg(guc, INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE); } static inline bool @@ -686,6 +697,24 @@ int intel_guc_reset_engine(struct intel_guc *guc, return ret; } +/* + * GuC notifies host that reset engine has completed. + * This message should only be received after a request-reset h2g, + * so check that and clear the engine_class_under_reset flag. + */ +static void guc_handle_engine_reset_completed(struct intel_guc *guc, + const u32 engine_class) +{ + if (engine_class >= GUC_MAX_ENGINE_CLASSES || + !guc_is_class_under_reset(guc, engine_class)) { + DRM_WARN("Unexpected reset-complete for engine class: %d", + engine_class); + return; + } + + guc_clear_class_under_reset(guc, engine_class); +} + /** * intel_guc_resume() - notify GuC resuming from suspend state * @guc: the guc diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 004d3d882f6f..3b037a9e3181 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -722,7 +722,8 @@ enum intel_guc_response_status { /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ enum intel_guc_recv_message { INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), - INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3) + INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3), + INTEL_GUC_RECV_MSG_ENGINE_RESET_COMPLETE = BIT(25), }; #endif From patchwork Fri Mar 29 22:11:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877861 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A252113B5 for ; Fri, 29 Mar 2019 22:12:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D20E28E8F for ; Fri, 29 Mar 2019 22:12:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 81AB0292AE; Fri, 29 Mar 2019 22:12:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 21F0F2906F for ; Fri, 29 Mar 2019 22:12:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E47176E57D; Fri, 29 Mar 2019 22:12:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id DE0116E569 for ; Fri, 29 Mar 2019 22:11:51 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="156522351" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga002.fm.intel.com with ESMTP; 29 Mar 2019 15:11:50 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0q017079; Fri, 29 Mar 2019 22:11:49 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:14 +0000 Message-Id: <20190329221118.17308-27-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 26/30] drm/i915/guc: Properly capture & release GuC interrupts on Gen11 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Oscar Mateo MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Oscar Mateo With the new interrupt re-partitioning in Gen11, GuC controls by itself the interrupts it receives, so steering bits and registers have been defeatured. Being this the case, when the GuC is in control of submissions we won't know what to do with the ctx switch interrupt in the driver, so disable it. Bspec: 12609 Bspec: 10800 Bspec: 10932 Bspec: 10934 Bspec: 9517 Signed-off-by: Oscar Mateo Signed-off-by: Michal Wajdeczko Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen Cc: Michal Winiarski --- drivers/gpu/drm/i915/i915_irq.c | 2 +- drivers/gpu/drm/i915/intel_guc_submission.c | 57 ++++++++++++++++++++- 2 files changed, 56 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 455b2bf691b5..4de6474b6a25 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -4634,7 +4634,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) <= 7) rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; - if (INTEL_GEN(dev_priv) >= 8) + if (INTEL_GEN(dev_priv) >= 8 && INTEL_GEN(dev_priv) < 11) rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c index b0b10cac9b9b..e3f6e2b1aa99 100644 --- a/drivers/gpu/drm/i915/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/intel_guc_submission.c @@ -1263,7 +1263,7 @@ void intel_guc_submission_fini(struct intel_guc *guc) guc_stage_desc_pool_destroy(guc); } -static void guc_interrupts_capture(struct drm_i915_private *dev_priv) +static void gen8_guc_interrupts_capture(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; struct intel_engine_cs *engine; @@ -1308,7 +1308,7 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv) rps->pm_intrmsk_mbz &= ~GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; } -static void guc_interrupts_release(struct drm_i915_private *dev_priv) +static void gen8_guc_interrupts_release(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; struct intel_engine_cs *engine; @@ -1333,6 +1333,59 @@ static void guc_interrupts_release(struct drm_i915_private *dev_priv) rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK; } +static void gen11_guc_interrupts_capture(struct drm_i915_private *dev_priv) +{ + struct intel_rps *rps = &dev_priv->gt_pm.rps; + u32 tmp; + u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT; + + /* Don't handle ctx switch interrupt in GuC submission mode */ + tmp = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); + tmp &= ~(irqs << 16 | irqs); + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, tmp); + + tmp = I915_READ(GEN11_VCS_VECS_INTR_ENABLE); + tmp &= ~(irqs << 16 | irqs); + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, tmp); + + /* GuC needs ARAT expired interrupt unmasked */ + rps->pm_intrmsk_mbz |= ARAT_EXPIRED_INTRMSK; +} + +static void gen11_guc_interrupts_release(struct drm_i915_private *dev_priv) +{ + struct intel_rps *rps = &dev_priv->gt_pm.rps; + u32 tmp; + u32 irqs = GT_CONTEXT_SWITCH_INTERRUPT; + + /* Handle ctx switch interrupts again */ + tmp = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); + tmp |= (irqs << 16 | irqs); + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, tmp); + + tmp = I915_READ(GEN11_VCS_VECS_INTR_ENABLE); + tmp |= (irqs << 16 | irqs); + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, tmp); + + rps->pm_intrmsk_mbz &= ~ARAT_EXPIRED_INTRMSK; +} + +static void guc_interrupts_capture(struct drm_i915_private *i915) +{ + if (INTEL_GEN(i915) >= 11) + gen11_guc_interrupts_capture(i915); + else + gen8_guc_interrupts_capture(i915); +} + +static void guc_interrupts_release(struct drm_i915_private *i915) +{ + if (INTEL_GEN(i915) >= 11) + gen11_guc_interrupts_release(i915); + else + gen8_guc_interrupts_release(i915); +} + static void guc_submission_park(struct intel_engine_cs *engine) { intel_engine_unpin_breadcrumbs_irq(engine); From patchwork Fri Mar 29 22:11:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877863 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 68DB917E0 for ; Fri, 29 Mar 2019 22:12:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5345128E8F for ; Fri, 29 Mar 2019 22:12:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 47CF2292AE; Fri, 29 Mar 2019 22:12:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C1DA028E8F for ; Fri, 29 Mar 2019 22:12:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2538E6E553; Fri, 29 Mar 2019 22:12:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 410676E56C for ; Fri, 29 Mar 2019 22:11:54 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="287130582" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga004.jf.intel.com with ESMTP; 29 Mar 2019 15:11:51 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0r017079; Fri, 29 Mar 2019 22:11:50 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:15 +0000 Message-Id: <20190329221118.17308-28-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 27/30] drm/i915/guc: Create vfuncs for the GuC interrupts control functions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Oscar Mateo MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Oscar Mateo Controlling and handling of the GuC interrupts is Gen specific. Create virtual functions to avoid redundant runtime Gen checks. Gen-specific versions of these functions will follow. Signed-off-by: Oscar Mateo Signed-off-by: Michal Wajdeczko Cc: Rodrigo Vivi Cc: Tvrtko Ursulin Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_drv.h | 22 ++++++++++++++++++++++ drivers/gpu/drm/i915/i915_irq.c | 18 ++++++++++++------ drivers/gpu/drm/i915/intel_drv.h | 3 --- drivers/gpu/drm/i915/intel_guc.h | 1 - drivers/gpu/drm/i915/intel_uc.c | 6 +++--- 5 files changed, 37 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3e7d0f3d2c82..120b0967c4e8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1580,6 +1580,13 @@ struct drm_i915_private { u32 pm_guc_events; u32 pipestat_irq_mask[I915_MAX_PIPES]; + struct { + bool enabled; + void (*reset)(struct drm_i915_private *i915); + void (*enable)(struct drm_i915_private *i915); + void (*disable)(struct drm_i915_private *i915); + } guc_interrupts; + struct i915_hotplug hotplug; struct intel_fbc fbc; struct i915_drrs drrs; @@ -2716,6 +2723,21 @@ extern void intel_irq_fini(struct drm_i915_private *dev_priv); int intel_irq_install(struct drm_i915_private *dev_priv); void intel_irq_uninstall(struct drm_i915_private *dev_priv); +static inline void intel_reset_guc_interrupts(struct drm_i915_private *i915) +{ + i915->guc_interrupts.reset(i915); +} + +static inline void intel_enable_guc_interrupts(struct drm_i915_private *i915) +{ + i915->guc_interrupts.enable(i915); +} + +static inline void intel_disable_guc_interrupts(struct drm_i915_private *i915) +{ + i915->guc_interrupts.disable(i915); +} + static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) { return dev_priv->gvt; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 4de6474b6a25..3dd971c09d52 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -535,7 +535,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) gen6_reset_rps_interrupts(dev_priv); } -void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv) +static void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv) { assert_rpm_wakelock_held(dev_priv); @@ -544,26 +544,26 @@ void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv) spin_unlock_irq(&dev_priv->irq_lock); } -void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv) +static void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv) { assert_rpm_wakelock_held(dev_priv); spin_lock_irq(&dev_priv->irq_lock); - if (!dev_priv->guc.interrupts_enabled) { + if (!dev_priv->guc_interrupts.enabled) { WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_guc_events); - dev_priv->guc.interrupts_enabled = true; + dev_priv->guc_interrupts.enabled = true; gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events); } spin_unlock_irq(&dev_priv->irq_lock); } -void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv) +static void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv) { assert_rpm_wakelock_held(dev_priv); spin_lock_irq(&dev_priv->irq_lock); - dev_priv->guc.interrupts_enabled = false; + dev_priv->guc_interrupts.enabled = false; gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events); @@ -4637,6 +4637,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) >= 8 && INTEL_GEN(dev_priv) < 11) rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; + if (INTEL_GEN(dev_priv) >= 9) { + dev_priv->guc_interrupts.reset = gen9_reset_guc_interrupts; + dev_priv->guc_interrupts.enable = gen9_enable_guc_interrupts; + dev_priv->guc_interrupts.disable = gen9_disable_guc_interrupts; + } + if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) dev->driver->get_vblank_counter = g4x_get_vblank_counter; else if (INTEL_GEN(dev_priv) >= 3) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f8c7b291fdc3..1739f2fe5288 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1618,9 +1618,6 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, u8 pipe_mask); void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv, u8 pipe_mask); -void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv); -void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv); -void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv); /* intel_crt.c */ bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index a4bc3355a753..47ec353ac666 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -56,7 +56,6 @@ struct intel_guc { /* intel_guc_recv interrupt related state */ spinlock_t irq_lock; - bool interrupts_enabled; unsigned int msg_enabled_mask; struct ida client_ids; diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index b516cc1ff18c..1e7ad200e761 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -223,7 +223,7 @@ static int guc_enable_communication(struct intel_guc *guc) { struct drm_i915_private *i915 = guc_to_i915(guc); - gen9_enable_guc_interrupts(i915); + intel_enable_guc_interrupts(i915); if (HAS_GUC_CT(i915)) return intel_guc_ct_enable(&guc->ct); @@ -240,7 +240,7 @@ static void guc_disable_communication(struct intel_guc *guc) if (HAS_GUC_CT(i915)) intel_guc_ct_disable(&guc->ct); - gen9_disable_guc_interrupts(i915); + intel_disable_guc_interrupts(i915); guc->send = intel_guc_send_nop; guc->handler = intel_guc_to_host_event_handler_nop; @@ -362,7 +362,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915) GEM_BUG_ON(!HAS_GUC(i915)); - gen9_reset_guc_interrupts(i915); + intel_reset_guc_interrupts(i915); /* WaEnableuKernelHeaderValidFix:skl */ /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */ From patchwork Fri Mar 29 22:11:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877845 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0C27817E0 for ; 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Fri, 29 Mar 2019 22:11:55 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="159699507" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga001.fm.intel.com with ESMTP; 29 Mar 2019 15:11:52 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0s017079; Fri, 29 Mar 2019 22:11:51 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:16 +0000 Message-Id: <20190329221118.17308-29-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 28/30] drm/i915/guc: Correctly handle GuC interrupts on Gen11 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Oscar Mateo MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Oscar Mateo The GuC interrupts now get their own interrupt vector (instead of sharing a register with the PM interrupts) so handle appropriately. Signed-off-by: Oscar Mateo Signed-off-by: Michal Wajdeczko Cc: Tvrtko Ursulin Cc: Daniele Ceraolo Spurio Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_drv.h | 6 ++- drivers/gpu/drm/i915/i915_irq.c | 76 +++++++++++++++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_guc_reg.h | 18 +++++++ 4 files changed, 94 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 120b0967c4e8..3b18fdbdea60 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1577,7 +1577,11 @@ struct drm_i915_private { u32 pm_imr; u32 pm_ier; u32 pm_rps_events; - u32 pm_guc_events; + union { + /* RPS and GuC share a register pre-Gen11 */ + u32 pm_guc_events; + u32 guc_events; + }; u32 pipestat_irq_mask[I915_MAX_PIPES]; struct { diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 3dd971c09d52..c1b4fbd5f496 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -573,6 +573,44 @@ static void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv) gen9_reset_guc_interrupts(dev_priv); } +static void gen11_reset_guc_interrupts(struct drm_i915_private *dev_priv) +{ + spin_lock_irq(&dev_priv->irq_lock); + + while (gen11_reset_one_iir(dev_priv, 0, GEN11_GUC)) + ; + + spin_unlock_irq(&dev_priv->irq_lock); +} + +static void gen11_enable_guc_interrupts(struct drm_i915_private *dev_priv) +{ + spin_lock_irq(&dev_priv->irq_lock); + if (!dev_priv->guc_interrupts.enabled) { + u32 guc_events = dev_priv->guc_events << 16; + + WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GUC)); + I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, guc_events); + I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~guc_events); + dev_priv->guc_interrupts.enabled = true; + } + spin_unlock_irq(&dev_priv->irq_lock); +} + +static void gen11_disable_guc_interrupts(struct drm_i915_private *dev_priv) +{ + spin_lock_irq(&dev_priv->irq_lock); + dev_priv->guc_interrupts.enabled = false; + + I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0); + I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0); + + spin_unlock_irq(&dev_priv->irq_lock); + synchronize_irq(dev_priv->drm.irq); + + gen11_reset_guc_interrupts(dev_priv); +} + /** * bdw_update_port_irq - update DE port interrupt * @dev_priv: driver private @@ -1823,6 +1861,12 @@ static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir) intel_guc_to_host_event_handler(&dev_priv->guc); } +static void gen11_guc_irq_handler(struct drm_i915_private *dev_priv, u16 iir) +{ + if (iir & GEN11_GUC_INTR_GUC2HOST) + intel_guc_to_host_event_handler(&dev_priv->guc); +} + static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) { enum pipe pipe; @@ -2945,11 +2989,17 @@ static void gen11_other_irq_handler(struct drm_i915_private * const i915, const u8 instance, const u16 iir) { - if (instance == OTHER_GTPM_INSTANCE) + switch (instance) { + case OTHER_GUC_INSTANCE: + return gen11_guc_irq_handler(i915, iir); + + case OTHER_GTPM_INSTANCE: return gen6_rps_irq_handler(i915, iir); - WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n", - instance, iir); + default: + WARN_ONCE(1, "unhandled other irq instance=0x%x, iir=0x%x\n", + instance, iir); + } } static void @@ -3469,6 +3519,8 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv) I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); + I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0); + I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0); } static void gen11_irq_reset(struct drm_device *dev) @@ -4111,6 +4163,10 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv) dev_priv->pm_imr = ~dev_priv->pm_ier; I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0); I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0); + + /* Same thing for GuC interrupts */ + I915_WRITE(GEN11_GUC_SG_INTR_ENABLE, 0); + I915_WRITE(GEN11_GUC_SG_INTR_MASK, ~0); } static void icp_irq_postinstall(struct drm_device *dev) @@ -4611,8 +4667,12 @@ void intel_irq_init(struct drm_i915_private *dev_priv) for (i = 0; i < MAX_L3_SLICES; ++i) dev_priv->l3_parity.remap_info[i] = NULL; - if (HAS_GUC_SCHED(dev_priv)) - dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT; + if (HAS_GUC_SCHED(dev_priv)) { + if (INTEL_GEN(dev_priv) < 11) + dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT; + else + dev_priv->guc_events = GEN11_GUC_INTR_GUC2HOST; + } /* Let's track the enabled rps events */ if (IS_VALLEYVIEW(dev_priv)) @@ -4637,7 +4697,11 @@ void intel_irq_init(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) >= 8 && INTEL_GEN(dev_priv) < 11) rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; - if (INTEL_GEN(dev_priv) >= 9) { + if (INTEL_GEN(dev_priv) >= 11) { + dev_priv->guc_interrupts.reset = gen11_reset_guc_interrupts; + dev_priv->guc_interrupts.enable = gen11_enable_guc_interrupts; + dev_priv->guc_interrupts.disable = gen11_disable_guc_interrupts; + } else if (INTEL_GEN(dev_priv) >= 9) { dev_priv->guc_interrupts.reset = gen9_reset_guc_interrupts; dev_priv->guc_interrupts.enable = gen9_enable_guc_interrupts; dev_priv->guc_interrupts.disable = gen9_disable_guc_interrupts; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8aee35ced574..d80661941723 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -290,6 +290,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define OTHER_CLASS 4 #define MAX_ENGINE_CLASS 4 +#define OTHER_GUC_INSTANCE 0 #define OTHER_GTPM_INSTANCE 1 #define MAX_ENGINE_INSTANCE 3 diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h index 7eba65795b58..a214f8b71929 100644 --- a/drivers/gpu/drm/i915/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/intel_guc_reg.h @@ -134,4 +134,22 @@ struct guc_doorbell_info { #define GUC_WD_VECS_IER _MMIO(0xC558) #define GUC_PM_P24C_IER _MMIO(0xC55C) +/* GuC Interrupt Vector */ +#define GEN11_GUC_INTR_GUC2HOST (1 << 15) +#define GEN11_GUC_INTR_EXEC_ERROR (1 << 14) +#define GEN11_GUC_INTR_DISPLAY_EVENT (1 << 13) +#define GEN11_GUC_INTR_SEM_SIG (1 << 12) +#define GEN11_GUC_INTR_IOMMU2GUC (1 << 11) +#define GEN11_GUC_INTR_DOORBELL_RANG (1 << 10) +#define GEN11_GUC_INTR_DMA_DONE (1 << 9) +#define GEN11_GUC_INTR_FATAL_ERROR (1 << 8) +#define GEN11_GUC_INTR_NOTIF_ERROR (1 << 7) +#define GEN11_GUC_INTR_SW_INT_6 (1 << 6) +#define GEN11_GUC_INTR_SW_INT_5 (1 << 5) +#define GEN11_GUC_INTR_SW_INT_4 (1 << 4) +#define GEN11_GUC_INTR_SW_INT_3 (1 << 3) +#define GEN11_GUC_INTR_SW_INT_2 (1 << 2) +#define GEN11_GUC_INTR_SW_INT_1 (1 << 1) +#define GEN11_GUC_INTR_SW_INT_0 (1 << 0) + #endif From patchwork Fri Mar 29 22:11:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877859 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5650F17E0 for ; Fri, 29 Mar 2019 22:12:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 43E1B28E8F for ; Fri, 29 Mar 2019 22:12:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3866B292B4; Fri, 29 Mar 2019 22:12:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4019228E8F for ; Fri, 29 Mar 2019 22:12:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 83D1A6E578; Fri, 29 Mar 2019 22:12:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 012D06E569 for ; Fri, 29 Mar 2019 22:11:53 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="156522374" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga002.fm.intel.com with ESMTP; 29 Mar 2019 15:11:53 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0t017079; Fri, 29 Mar 2019 22:11:52 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:17 +0000 Message-Id: <20190329221118.17308-30-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 29/30] HAX: prevent CI failures on pre-Gen11 configs with forced GuC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Some Gen9 CI systems are still prepared to run no longer supported configuration "enable_guc=3" Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/intel_uc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 1e7ad200e761..a522889c542f 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -109,6 +109,10 @@ static void sanitize_options_early(struct drm_i915_private *i915) struct intel_uc_fw *guc_fw = &i915->guc.fw; struct intel_uc_fw *huc_fw = &i915->huc.fw; + /* HAX: prevent CI failures on pre-Gen11 configs with forced GuC */ + if (i915_modparams.enable_guc && INTEL_GEN(i915) < 11) + i915_modparams.enable_guc &= ~ENABLE_GUC_SUBMISSION; + /* A negative value means "use platform default" */ if (i915_modparams.enable_guc < 0) i915_modparams.enable_guc = __get_platform_enable_guc(i915); From patchwork Fri Mar 29 22:11:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Wajdeczko X-Patchwork-Id: 10877857 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E871917E0 for ; Fri, 29 Mar 2019 22:12:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D564F28E8F for ; Fri, 29 Mar 2019 22:12:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CA214292AE; Fri, 29 Mar 2019 22:12:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8236428E8F for ; Fri, 29 Mar 2019 22:12:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B568E6E54D; Fri, 29 Mar 2019 22:12:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id B204A6E56D for ; Fri, 29 Mar 2019 22:11:54 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 15:11:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,286,1549958400"; d="scan'208";a="127065420" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by orsmga007.jf.intel.com with ESMTP; 29 Mar 2019 15:11:53 -0700 Received: from mwajdecz-MOBL1.ger.corp.intel.com (mwajdecz-mobl1.ger.corp.intel.com [10.249.137.139]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id x2TMBN0u017079; Fri, 29 Mar 2019 22:11:52 GMT From: Michal Wajdeczko To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 22:11:18 +0000 Message-Id: <20190329221118.17308-31-michal.wajdeczko@intel.com> X-Mailer: git-send-email 2.10.1.windows.1 In-Reply-To: <20190329221118.17308-1-michal.wajdeczko@intel.com> References: <20190329221118.17308-1-michal.wajdeczko@intel.com> Subject: [Intel-gfx] [PATCH 30/30] HAX: Enable HuC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP For now, we only want to test "enable_guc=2" configuration. Signed-off-by: Michal Wajdeczko --- drivers/gpu/drm/i915/i915_params.h | 2 +- drivers/gpu/drm/i915/intel_uc.c | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 3f14e9881a0d..e28ae23de516 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -54,7 +54,7 @@ struct drm_printer; param(int, disable_power_well, -1) \ param(int, enable_ips, 1) \ param(int, invert_brightness, 0) \ - param(int, enable_guc, 0) \ + param(int, enable_guc, -1) \ param(int, guc_log_level, -1) \ param(char *, guc_firmware_path, NULL) \ param(char *, huc_firmware_path, NULL) \ diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index a522889c542f..d13597246302 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -67,6 +67,9 @@ static int __get_platform_enable_guc(struct drm_i915_private *i915) if (INTEL_GEN(i915) < 11) enable_guc &= ~ENABLE_GUC_SUBMISSION; + /* HAX: Never allow GuC submission */ + enable_guc &= ~ENABLE_GUC_SUBMISSION; + return enable_guc; }