[0/7] target/riscv: store max SATP mode as a single integer in RISCVCPUConfig

Message

Paolo Bonzini Feb. 18, 2025, 4:57 p.m. UTC

The maximum available SATP mode implies all the shorter virtual address sizes.
Simplify the handling of the satp_mode field in RISCVCPUConfig:

- store a single byte in RISCVCPUConfig for the maximum supported size,
  and adjust it to the maximum requested size based on QOM properties

- move satp_mode.{map,init} out of RISCVCPUConfig since they are
  only needed to implement the user-friendly properties for -cpu

The benefit is that code outside target/riscv/ does not need to call
satp_mode_max_from_map() anymore, it can just check cpu->cfg.max_satp_mode.

The first three patches are independent bugfixes.

This series is a spin off of "target/riscv: declarative CPU definitions"
(https://lore.kernel.org/qemu-devel/[e-mail]/T/#t).

Paolo

Paolo Bonzini (7):
  hw/riscv: acpi: only create RHCT MMU entry for supported types
  target/riscv: env->misa_mxl is a constant
  target/riscv: assert argument to set_satp_mode_max_supported is valid
  target/riscv: cpu: store max SATP mode as a single integer
  target/riscv: update max_satp_mode based on QOM properties
  target/riscv: remove supported from RISCVSATPMap
  target/riscv: move satp_mode.{map,init} out of CPUConfig

 target/riscv/cpu.h         | 15 +++++-
 target/riscv/cpu_cfg.h     | 17 +------
 hw/riscv/virt-acpi-build.c | 15 +++---
 hw/riscv/virt.c            |  5 +-
 target/riscv/cpu.c         | 98 +++++++++++++++++++++-----------------
 target/riscv/csr.c         |  9 +++-
 target/riscv/machine.c     | 13 +++++
 target/riscv/tcg/tcg-cpu.c |  3 +-
 8 files changed, 100 insertions(+), 75 deletions(-)