Show patches with: Series = target/riscv: store max SATP mode as a single integer in RISCVCPUConfig       |    State = Action Required       |    Archived = No       |   7 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[7/7] target/riscv: move satp_mode.{map,init} out of CPUConfig target/riscv: store max SATP mode as a single integer in RISCVCPUConfig - - - --- 2025-02-18 Paolo Bonzini New
[6/7] target/riscv: remove supported from RISCVSATPMap target/riscv: store max SATP mode as a single integer in RISCVCPUConfig - - - --- 2025-02-18 Paolo Bonzini New
[5/7] target/riscv: update max_satp_mode based on QOM properties target/riscv: store max SATP mode as a single integer in RISCVCPUConfig - - - --- 2025-02-18 Paolo Bonzini New
[4/7] target/riscv: cpu: store max SATP mode as a single integer target/riscv: store max SATP mode as a single integer in RISCVCPUConfig - - - --- 2025-02-18 Paolo Bonzini New
[3/7] target/riscv: assert argument to set_satp_mode_max_supported is valid target/riscv: store max SATP mode as a single integer in RISCVCPUConfig - - - --- 2025-02-18 Paolo Bonzini New
[2/7] target/riscv: env->misa_mxl is a constant target/riscv: store max SATP mode as a single integer in RISCVCPUConfig - - - --- 2025-02-18 Paolo Bonzini New
[1/7] hw/riscv: acpi: only create RHCT MMU entry for supported types target/riscv: store max SATP mode as a single integer in RISCVCPUConfig - - - --- 2025-02-18 Paolo Bonzini New